ADP3410 Analog Devices, ADP3410 Datasheet - Page 4

• Manufacturer Part Number: ADP3410
• Description: Dual MOSFET Driver with Bootstrapping
• Manufacturer: Analog Devices

ADP3410
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
OVPSET
SD
GND
IN
DRVLSD
DLY
VCCGD
VCC
DRVL
PGND
SRMON
SW
DRVH
BST
Function
Overvoltage Shutdown Sense Input. Shutdown occurs when this pin is driven above the specified thresh-
old. It is a high-impedance comparator input, so an external resistor divider can be used to scale the
controlling voltage for OVP.
Shutdown. When high, this pin enables normal operation. When low, VCCGD, DRVH, and DRVL are
forced low and the supply current (ICC
Signal Ground. The input signal and the capacitor at DLY should be closely referenced to this ground.
TTL-level input signal which has primary control of the drive outputs.
Synchronous Rectifier Enable. When low, this signal forces DRVL low. The propagation delay time is on
the order of that for the main input signal, so it can be used for real time modulation control of DRVL.
When DRVLSD is high, DRVL is enabled and controlled by IN.
Low-High-Transition Delay. A capacitor from this pin to ground programs the propagation delay
from turn-off of the lower FET to turn-on of the upper FET. The formula for the low-high-transition
delay is DLY = C
the formula.
V
device to exit UVLO mode, the VCCGD pin is pulled up to V
signal is capable of acting as a switched power rail for external circuitry, since it can source 10 mA and
sink 10 A.
Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.
Power Ground. Should be closely connected to the source of the lower FET.
Synchronous Rectifier Monitor. When DRVLSD is high, SRMON follows DRVL. When DRVLSD is
low, SRMON is high. TTL-type output.
This pin is connected to the buck switching node, close to the upper FET’s source. It is the floating return
for the upper FET drive signal. Also, it is used to monitor the switched voltage to prevent turn-on of the
lower FET until the voltage is below ~1 V. Thus, the high-low-transition delay is determined at this pin
according to operating conditions. This pin can be subjected to voltages as low as 2 V below PGND.
Buck Drive. Output drive for the upper (buck) FET.
Floating Bootstrap Supply for the upper FET. A capacitor connected between BST and SW pins holds
this bootstrapped voltage for the high-side FET as it is switched. The capacitor should be chosen between
0.1 F and 1 F.
CC
Good. This pin indicates the status of the undervoltage lockout. When V
DLY
PIN FUNCTION DESCRIPTIONS
DRVLSD
(1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in
OVPSET
VCCGD
PIN CONFIGURATION
GND
DLY
SD
IN
ADP3410
1
2
3
4
5
6
7
–4–
Q
) is minimized as specified.
14
13
12
11
10
9
8
BST
DRVH
SW
SRMON
PGND
DRVL
VCC
CC
with the specified low impedance. This
CC
is high enough for the
REV. 0