ADP3164 Analog Devices, ADP3164 Datasheet - Page 13

• Manufacturer Part Number: ADP3164
• Description: 5-Bit Programmable 4-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

The ripple voltage across the three paralleled capacitors is:
Multilayer ceramic input capacitors are also required. These
capacitors should be placed between the Input side of the cur-
rent sense resistor and the sources of the low-side synchronous
MOSFETs. These capacitors decouple the high-frequency lead-
ing edge current spike that supplies the reverse recovery charge
of the low-side MOSFET’s body diode. The exact number
required is a function of the board layout. Typical designs will
use two 10 µF MLC capacitors. To reduce the input-current di/
dt to below the recommended maximum of 0.1 A/µs, an addi-
tional small inductor (L > 1 µH @ 15 A) should be inserted
between the converter and the supply bus. That inductor also
acts as a filter between the converter and the primary power source.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system.
General Recommendations
1.
2.
3.
4.
5.
6.
V
80
C RIPPLE
For good results, at least a four-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 12 V), and wide interconnection traces in the
rest of the power delivery current paths. Keep in mind that
each square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro-
duced by these current paths is minimized and the via
current rating is not exceeded.
If critical signal lines (including the voltage and current
sense lines of the ADP3164) must cross through power
circuitry, it is best if a signal ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
The power ground plane should not extend under signal
components, including the ADP3164 itself. If necessary,
follow the preceding guideline to use the signal ground
plane as a shield between the power ground plane and the
signal circuitry.
The GND pin of the ADP3164 should be connected first to
the timing capacitor (on the CT pin), and then into the
signal ground plane. In cases where no signal ground plane
can be used, short interconnections to other signal ground
circuitry in the power converter should be used.
The output capacitors of the power converter should be
connected to the signal ground plane even though power
4
(
A
×



)
18
=
3
m
I
n
O
Ω
×
+



3 270
ESR
×
n
C
C
+
µ
0 123
n
F
.
C
×
×
200
C
D
IN
HSF
kHz
×
f
SW

 =


 =

135
mV
(26)
7.
8.
Power Circuitry
9.
10. MLC input capacitors should be placed between V
11. To dampen ringing, an RC Snubber circuit should be placed
12. An optional power Schottky diode (3 A–5 A dc rating)
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections
(e.g., the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It is
also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors should also be distributed, and generally in pro-
portion to where the load tends to be more dynamic.
Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precautions often results in EMI problems for the
entire PC system as well as noise-related operational problems
in the power converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors, the power MOSFETs, and the power
Schottky diode, if used (see next), including all intercon-
necting PCB traces and planes. The use of short and wide
interconnection traces is especially critical in this path for
two reasons: it minimizes the inductance in the switching
loop, which can cause high-energy ringing, and it accommo-
dates the high current demand with minimal voltage loss.
Power Ground as close as possible to the sources of the
low-side MOSFETs.
from the SW node of each phase to ground.
from each lower MOSFET’s source (anode) to drain (cath-
ode) will help to minimize switching power dissipation in
the upper MOSFETs. In the absence of an effective Schot-
tky diode, this dissipation occurs through the following
sequence of switching events. The lower MOSFET turns
off in advance of the upper MOSFET turning on (necessary
to prevent cross-conduction). The circulating current in
the power converter, no longer finding a path for current
through the channel of the lower MOSFET, draws cur-
rent through the inherent body diode of the MOSFET. The
upper MOSFET turns on, and the reverse recovery charac-
teristic of the lower MOSFET’s body diode prevents the
drain voltage from being pulled high quickly. The upper
MOSFET then conducts very large current while it momen-
tarily has a high voltage forced across it, which translates
into added power dissipation in the upper MOSFET. The
Schottky diode minimizes this problem by carrying a major-
ity of the circulating current when the lower MOSFET is
turned off, and by virtue of its essentially nonexistent
reverse recovery time. The Schottky diode has to be con-
nected with very short copper traces to the MOSFET to
be effective.
ADP3164
IN
and