ADP3162 Analog Devices, ADP3162 Datasheet - Page 9

• Manufacturer Part Number: ADP3162
• Description: 5-Bit Programmable 2-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

Choosing the nearest 1% resistor gives R
R
Choosing the nearest 1% resistor gives R
C
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. The ESR of the output filter capacitor bank must be equal
to or less than the specified output resistance (3.2 mΩ) of the
voltage regulator. The capacitance must be large enough that
the voltage across the capacitor, which is the sum of the resistive
and capacitive voltage drops, does not moves below or above the
initial resistive step while the inductor current ramps up or
down to the value corresponding to the new load current.
One can use, for example, four SP-Type OS-CON capacitors
from Sanyo, with 820 µF capacitance, a 4 V voltage rating,
and 12 mΩ ESR. The four capacitors have a maximum total
ESR of 3 mΩ when connected in parallel. Another possibility is
the ZA series from Rubycon. The trade-off is size versus cost.
Eight 1000 µF capacitors would give an ESR of 3 mΩ. These
eight capacitors take up more space than four OS-CON capaci-
tors, but are significantly less expensive.
As long as the capacitance of the output capacitor is above a
critical value and the regulating loop is compensated with
Analog Devices’ proprietary compensation technique, ADOPT,
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
The critical capacitance can be calculated as follows:
The equivalent capacitance of the four OS-CON capacitors is
4 × 820 µF = 3.28 mF, and the equivalent capacitance of the
eight ZA series Rubycon capacitors is 8 mF. With both choices,
the total capacitance is safely above the critical value.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3162 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
The output current slew rate of any practical switching power
converter is inherently limited by the inductor to a value much
less than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
R
A
A
OUT
R
R
is calculated:
=
B
B
C
3 2
R
Selection
=
=
1
OUT CRIT
.
T
V
−
3
m
REF
(
V
R
Ω
28
OGM
7 1
1
1
−
R
×
.
−
1 194
T
)
A
1 755
V
.
k
−
=
.
GNL
Ω
R
R
1
B
OUT
V
V
=
−
V
7 1
g
−
I
×
REF
.
×
m
3
O
2 2
1
V
1
V
×
.
k
Ω
OFL
µ
2
(
V
mmho
H
−
ONL
200
×
=
L
2 49
1
2
−
1
k
×
.
V
Ω
45
OUT
−
mF
19 1
mV
B
A
)
= 19.1 kΩ. Finally,
= 12.1 kΩ.
.
1
k
=
Ω
19 31
=
.
11 98
.
k
Ω
k
Ω
(12)
(11)
(13)
larger than the critical value defined by Equation 14, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range—
including dc—and equal to the specified dc output resistance.
With the wide-band resistive output impedance the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning and
allows the minimization of the output capacitor.
With an ideal current-mode controlled converter, where the
inductor current would respond without delay to the command
signal, the resistive output impedance could be achieved by having
a single-pole roll-off of the voltage gain of the voltage-error
amplifier. The pole frequency must coincide with the ESR zero
of the output capacitor. The ADP3162 uses constant-frequency
peak-current control, which is known to have a nonideal, frequency
dependent command-signal-to-inductor-current transfer func-
tion. The frequency dependence manifests in the form of a pair
of complex conjugate poles at one-half of the switching frequency.
A purely resistive output impedance could be achieved by can-
celing the complex conjugate with zeros at the same complex
frequencies and adding a third pole equal to the ESR zero of the
output capacitor. Such a compensating network would be quite
complicated. Fortunately, in practice it is sufficient to cancel the
pair of complex conjugate poles with a single real zero placed at
one-half of the switching frequency. Although the end result is
not a perfectly resistive output impedance, the remaining fre-
quency dependence causes only a few percentage of deviation
from the ideal resistive response. The single-pole and single-zero
compensation can be easily implemented by terminating the g
error amplifier with the parallel combination of a resistor (R
and a series RC network. The value of the terminating resistor
R
the series RC network are calculated as follows:
For the Rubycon output capacitors, the compensating capaci-
tor is:
The closest standard value is 3.3 nF.
The nearest standard 5% resistor value is 470 Ω. Note that this
resistor is only required when C
25% or less). In this example C
fore be omitted.
Power MOSFETs
In the standard two-phase application two pairs of N-channel
power MOSFETs must be used with the ADP3162 and ADP3412,
one pair as the main (control) switches, and the other pair as
the synchronous rectifier switches. The main selection parameters
for the power MOSFETs are V
mum gate drive voltage (the supply voltage to the ADP3412)
T
was determined previously; the capacitance and resistance of
C
C
R
OC
OC
Z
=
=
=
C
8
C
OC
mF
OUT
7 1
× ×
.
π
R
2
×
×
k
T
3
Ω
R
m
f
OUT
OSC
Ω
−
=
−
π
3 3
π
×
.
×
400
OUT
nF
f
GS(TH)
OSC
OUT
2
kHz
× ×
>> C
π
2
×
approaches C
2
R
and R
×
T
400
CRIT
7 1
.
kHz
k
, and R
ADP3162
DS(ON)
Ω
=
=
3 16
. The mini-
CRIT
483
.
Z
can there-
nF
Ω
(within
T
(14)
(15)
)
m