USB2228 SMSC Corporation, USB2228 Datasheet - Page 17

• Manufacturer Part Number: USB2228
• Description: (USB2227 / USB2228) 4th Generation USB2.0 Flash Media Controller
• Manufacturer: SMSC Corporation

4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs
Datasheet
SMSC USB2227/USB2228
MA[1:0]/CLK_
SEL_CLKDR
SYMBOL
SEL[1:0]
nMWR
nMRD
MA2/
V
128-PIN
VTQFP
118
117
116
14
13
124-PIN
DQFN
A59
B55
A58
B7
A7
BUFFER
I/O8PD
I/O8PD
TYPE
O8
O8
DATASHEET
17
Memory Address Bus:
MA2 Addresses memory locations within the external
memory.
SEL_CLKDRV. During nRESET assertion, this pins will
select the operating clock mode (crystal or externally
driven clock source), and a weak pull-down resistor is
enabled. When nRESET is negated, the value will be
internally latched and this pin will revert to MA2
functionality, the internal pull-down will be disabled.
‘0’ = Crystal operation (24MHz only)
‘1’ = Externally driven clock source (24MHz or 48MHz)
Note:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the MA2 pin will function
identically to the MA[15:3] pins at all times (other than
during nRESET assertion).
Memory Address Bus:
MA[1:0], These signals address memory locations within
the external memory.
SEL[1:0]. During nRESET assertion, these pins will
select the operating frequency of the external clock, and
the corresponding weak pull-down resistors are enabled.
When nRESET is negated, the value on these pins will
be internal latched and these pins will revert to MA[1:0]
functionality, the internal pull-downs will be disabled.
SEL[1:0] = ‘00’. 24MHz
SEL[1:0] = ‘01’. RESERVED
SEL[1:0] = ‘10’. RESERVED
SEL[1:0] = ‘11’. 48MHz
Note:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the corresponding MA pin
will function identically to the MA[15:3] pins at all times
(other than during nRESET assertion).
Memory Write Strobe:
Program Memory Write; active low
Memory Read Strobe:
Program Memory Read; active low
If the latched value is ‘1’, then the MA2 pin is
tri-stated when the following conditions are
true:
If the latched value is ‘1’, then the
corresponding MA pin is tri-stated when the
following conditions are true:
DESCRIPTION
Revision 1.91 (10-13-06)