ACS8595 Semtech Corporation, ACS8595 Datasheet - Page 8

• Manufacturer Part Number: ACS8595
• Description: Line Card Protection Switch for Sonet/sdh Advancedtca Systems
• Manufacturer: Semtech Corporation

The Sync inputs (SYNC1, SYNC2 and SYNC3) are used for
Frame Sync output alignment and can be 2, 4 or 8 kHz
(automatically detected frequency).
As in all the Semtech ACS85xx series of parts supporting
such a mechanism, the Sync is treated as an additional
part of the SEC clock. The failure of a Sync input will never
cause a source disqualification. The Sync input is used to
internally align the generation of the output 2 kHz and
8 kHz Sync pulses.
Serial Interface
The ACS8595 device has an SPI compatible serial
interface, providing access to the configuration and
status registers for device set-up and monitoring.
Performance
Conformance
The ACS8595 is designed for use in Line Cards in Network
Elements which must meet the requirements of the
following specifications:
ITU: G. 736, G.742, G.812, G.813, G.824, K.41.
Telcordia: GR-253-CORE, GR-499-CORE, GR-1244-CORE.
ANSI: T1.101-1999.
ETSI: ETSI 300 462-3, ETSI 300 462-5.
Typical Application
Figure 3 Semtech’s Product Family Solution for a Typical SONET/SDH Architecture
Revision 2.00/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Backplane
Master Clock
Master Sync
Slave Clock
Slave Sync
Stand-by Clock
Stand-by Sync
Primary Ref.
Input/
output
Master Sync Card
Line Card (0C-12, OC-48)
Recovered Clock
LINE
CARD
PROTECTION
ACS8595 ATCA
Slave Sync Card
Line
Unit
I/F
ACS8525
ACS8526
ACS8515
ACS8527
Low Jitter up to 622 MHz
DATA
DATA
CLK
SSM
ACS8942A
JAM PLL
SSM Handling
Function
mP/Serial Bus
Multi Frame Sync
FINAL
Frame Sync
Priorities
Page 8
Input CLK Sources
E1/DS1
Clock
Distribution
Performance Benefits from DPLL/APLL Technology
The use of Digital Phase Locked Loop technology ensures
precise and repeatable performance over temperature or
voltage variations, and between parts. The overall PLL
bandwidth, loop damping, pull-in range and frequency
accuracy are all determined by digital parameters that
provide a consistent level of performance. An Analog PLL
takes the signal from the DPLL output and provides a
lower jitter output. The APLL bandwidth is set four orders
of magnitude higher than the DPLL bandwidth. This
ensures that the overall system performance still
maintains the advantage of consistent behavior provided
by the digital approach.
The DPLLs are clocked by the external oscillator module
therefore the Free-run or Digital Holdover frequency
stability is only determined by the stability of the external
oscillator module. This key advantage confines all
temperature critical components to one well defined and
pre-calibrated module, whose performance can be
chosen to match the application.
All performance parameters of the DPLLs are
programmable without the need to understand detailed
PLL equations. Bandwidth, damping factor and lock
range, for example, can all be set directly.
A high level of phase and frequency accuracy is made
possible in the ACS8595 by an internal resolution of up to
54 bits and internal Holdover accuracy of up to
7.5 x 10
SEC
Priorities
Config.
TCLK
FRAMER
Clock
Distribution
Low Jitter/Low Skew
SETS
-14
ppb (instantaneous).
ACS8510
ACS8520
ACS8522
ACS8530
SERDES
Output
CLKs
Multiple Line cards
To/from
SONET/SDH/PDH
Network
SetsLinecardGenApp_08
ACS8595 ATCA
PRODUCT BRIEF
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