ACS8530 Semtech Corporation, ACS8530 Datasheet - Page 116

• Manufacturer Part Number: ACS8530
• Description: Synchronous Equipment Timing Source For Stratum 2/3E/3 Systems
• Manufacturer: Semtech Corporation

Address (hex):
Address (hex):
Revision 3.01/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[7:5]
[4:0]
Bit 7
[6:4]
7
69
6A
cnfg_T0_DPLL_acq_bw
Description
Not used.
T0_DPLL_acquisition_bandwidth
Register to configure the bandwidth of the T0 DPLL
when acquiring phase lock on an input reference.
Reg. 3B Bit 7 is used to control whether this
bandwidth is not used or automatically switched to
when not phase locked.
cnfg_T4_DPLL_damping
Description
Not used.
T4_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6C Bit 7,
cnfg_T4_DPLL_PD2_gain.
Bit 6
Bit 6
T4_PD2_gain_alog_8k
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 116
(R/W) Register to configure the
bandwidth of the T0 DPLL, when
not phase locked to an input.
(R/W) Register to configure the
damping factor of the T4 DPLL,
along with the gain of Phase
Detector 2 in some modes.
10010-11111
Bit Value
Bit Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
Bit 3
Bit 3
-
-
-
T0_DPLL_acquisition_bandwidth
Value Description
-
T0 DPLL 0.5 mHz acquisition bandwidth.
T0 DPLL 1 mHz acquisition bandwidth.
T0 DPLL 2 mHz acquisition bandwidth.
T0 DPLL 4 mHz acquisition bandwidth.
T0 DPLL 8 mHz acquisition bandwidth.
T0 DPLL 15 mHz acquisition bandwidth.
T0 DPLL 30 mHz acquisition bandwidth.
T0 DPLL 60 mHz acquisition bandwidth.
T0 DPLL 0.1 Hz acquisition bandwidth.
T0 DPLL 0.3 Hz acquisition bandwidth.
T0 DPLL 0.6 Hz acquisition bandwidth.
T0 DPLL 1.2 Hz acquisition bandwidth.
T0 DPLL 2.5 Hz acquisition bandwidth.
T0 DPLL 4 Hz acquisition bandwidth.
T0 DPLL 8 Hz acquisition bandwidth.
T0 DPLL 18 Hz acquisition bandwidth.
T0 DPLL 35 Hz acquisition bandwidth.
T0 DPLL 70 Hz acquisition bandwidth.
Not used.
Value Description
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
Bit 2
Bit 2
Default Value
Default Value
ACS8530 SETS
T4_damping
Bit 1
Bit 1
DATASHEET
www.semtech.com
0000 1111
0001 0011
Bit 0
Bit 0