ACS411CS Semtech Corporation, ACS411CS Datasheet - Page 22

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ACS411CS

Manufacturer Part Number
ACS411CS
Description
Acapella Optical Modem ic
Manufacturer
Semtech Corporation
Datasheet
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
Table 15 shows the memory map of the ACS4110. The
location names are chosen to match the corresponding
pin names. Signals not directly equivalent to pins are in
lower case.
The device identification number id<7:0> on address
0x00 is used in EPROM mode to check if an external
memory device is connected. The value to be
programmed is 0xAA.
The whole chip set-up except DR<3:1> can be
controlled individually for each channel.
Memory Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Bit
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7
6-4
3
2
1
0
7
6-4
3
2-0
7-0
7-0
7-0
7-0
7-2
1
0
7
6
5
4
3
2
1
0
7-0
7-0
7-0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R
R
R
R
-
R
R
R
R
R/W
-
R/W
R/W
R
R
R/W
R/W
-
trsel<8:1>
trsel<16:9>
resel<16:9>
rl_det<8:1>
ll_det<8:1>
tm<7:0>
Name
id<7:0>
ch_enb<8:1>
ch_enb<16:9> Channel enable (active low) for channels 9 to 16.
cm1<8:1>
cm1<16:9>
cm2<8:1>
cm2<16:9>
cm3<8:1>
cm3<16:9>
pol1<8:1>
pol1<16:9>
pol2<8:1>
pol2<16:9>
pol3<8:1>
pol3<16:9>
ckc<8:1>
ckc<16:9>
resel<8:1>
cm_m<3:1>
CKLOCAL
CKM
trsel_m
resel_m
MSEL<3:1>
ENRSB
DR<3:1>
rl_det<16:9>
ll_det<16:9>
rlm_det
llm_det
DCD
LOSS
ERRL
fail_ne
fail_fe
resync_ne
resync_fe
errc<7:0>
Table 15: Memory Map
22
Description
Line code polarity POL bit 1 for channels 9 to 16.
Line code polarity POL bit 2 for channels 1 to 8.
Line code polarity POL bit 2 for channels 9 to 16.
Line code polarity POL bit 3 for channels 1 to 8.
Line code polarity POL bit 3 for channels 9 to 16.
Transmit clock edge select for maintenance channel.
Receive clock edge select for maintenance channel.
Maintenance channel data rate select.
Data rate select.
Far-end local loop-back detect channels 9 to 16.
Near-end remote loop-back detect for maintenance channel.
Far-end local loop-back detect for maintenance channel.
Alarm indication for near-end receive fail.
Alarm indication for far-end receive fail.
8-bit saturating error counter (reset by write).
The error counter errc<7:0> (address 0x1D) is an 8-bit
saturating counter for the ERRC error pulse. A write of
a 0x00 mask to this address clears the counter to 0x00.
The status signals ERRL, fail_ne, fail_fe can also be
cleared by writing a 0 to the specific bit in the address.
For example, writing a mask of 0xDF to address 0x1C
clears the ERRL signal, but leaves other status signals
unchanged.
If the microprocessor interface is enabled (UPSEL /=
0), the default start-up values of all control bits except
POL(3:1) and CKLOCAL are taken over from the pin
values as default during reset.
Device identification number.
Channel enable (active low) for channels 1 to 8.
Configuration mode CM bit 1 for channels 1 to 8.
Configuration mode CM bit 1 for channels 9 to 16.
Configuration mode CM bit 2 for channels 1 to 8.
Configuration mode CM bit 2 for channels 9 to 16.
Configuration mode CM bit 3 for channels 1 to 8.
Configuration mode CM bit 3 for channels 9 to 16.
Line code polarity POL bit 1 for channels 1 to 8.
Clock direction select for channels 1 to 8.
Clock direction select for channels 9 to 16.
Transmit clock edge select for channels 1 to 8.
Transmit clock edge select for channels 9 to 16.
Receive clock edge select for channels 1 to 8.
Receive clock edge select for channels 9 to 16.
Configuration mode CM for maintenance channel.
Local Tx/Rx CLK setup in remote control mode
Clock direction select maintenance channel.
Enable remote control setup.
Near-end remote loop-back detect channels 1 to 8.
Near-end remote loop-back detect channels 9 to 16.
Far-end local loop-back detect channels 1 to 8.
Data carrier detect status.
Loss of signal status.
Error latch.
Near-end device has entered re-synchronization.
Far-end device has entered re-synchronization.
Test mode select.

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