ACS104A Semtech Corporation, ACS104A Datasheet - Page 4

• Manufacturer Part Number: ACS104A
• Description: Acs104a Fiber Modem
• Manufacturer: Semtech Corporation

the communicating modems will achieve synchronisation with one
establishing itself as an active lock modem and the other
establishing itself as a drift lock modem. On subsequent attempts to
lock, synchronisation will be achieved within 3 seconds. It is only
necessary to apply reset to one device in the communicating pair to
initiate an arbitration process.
Since memory lock uses on-chip storage, loss of power to the
modem will require a new reset (PORB=0). Furthermore, should
there be a need to synchronise with a third modem a reset will again
be required.
Mixing Lock modes
It is possible to mix all combinations of locking modes once the
modems are locked, however, prior to synchronisation two modems
configured in active lock will not operate.
locking modes on locking speed is given in Table 4 :
Device A
Mode
Drift
Drift
Drift
Drift
Active
Active
Active
Random
Random
Memory
Table 4. Mixing lock modes
The Power-On Reset or PORB resets the device if forced Low for
100ms or more. This pin should be connected as figure 4.
Normally, a parallel resonant crystal will be connected between the
pins XLI and XLO with the appropriate padding capacitors. The
crystal oscillator will operate with padding capacitors of value 0 -
50pF, and the designer should endeavour to use padding capacitors
of low value since this will ensure the lowest power consumption.
The ACS104A has been designed to operate with a crystal tolerance
of +/- 250ppm giving a relative tolerance between communicating
modem pairs of 500 ppm. This wide tolerance will support the use of
low value padding capacitors.
Alternatively, XLI may be driven directly by an external clock. The
clock frequency for the purpose of this specification is referred to as
the XTAL frequency. The operational range for the XTAL frequency
is 5 - 27MHz, though communicating devices must use the same
nominal value.
The Data Carrier Detect (DCDB) signal goes Low when the modems
are synchronised ('locked') and ready for data transmission. Prior to
lock (DCDB = High), the data channel output RxD will be forced Low
and the handshake outputs CTS and DSR will be forced High.
The status of DCDB is also given by the HBT pin. See section
headed HBT Status pin.
The CNT value is inversely proportional to the XTAL frequency. The
capacitor is connected between pins CNT and GND.
tolerance on CNT is sufficient. For a XTAL frequency range of
5 to 27MHz the recommended value of the capacitor on CNT is from
47nF at 5MHz, 22nF at 10Hz down to 10nF at 27MHz . A ceramic
type is required to ensure low leakage. The CNT capacitor value
has an effect on the initial locking time and the receiver sensitivity
limit. Higher values giving improved sensitivity and lower values
giving faster locking.
This signal can be used to give an indication of the quality of the
optical link. Even when a DC signal is applied to the data and
handshake inputs, the ACS104A modem transmits up to 200kbps
over the link in each direction. This control data is used to maintain
PORB
Crystal Clock
DCDB
CNT Capacitor
ERL (Error Detector)
Advanced Communications
Device B
Mode
Drift
Active
Random
Memory
Active
Random
Memory
Random
Memory
Memory
Locking Speed
Drift
Active
Random
Random
Not allowed
Random
Random
Random
Random
Active
(Random on first synchronisation)
The effect of mixing
A
20 %
4
the timing and the relative positioning of 'transmit' and 'receive'
windows.
The transmit and control data is constantly monitored to make sure it
is compatible with the 3B4B format. If a coding error is detected,
ERL will go High and will remain High until reset. ERL may be reset
by asserting PORB, or by removing the fiber-optic cable from one
side of the link thereby forcing the device temporarily out of lock.
Please note that ERL detects coding errors and not data errors,
nevertheless because of the complexity of the coding rules on the
ACS104A the absence of detected errors on this pin will give a good
indication of a high quality link.
The ACS104A HBT pin affords a method of driving a display LED in
a manner which is sympathetic to low power consumption. The HBT
pin is pulsed to indicate 'locked' status (DCDB = 0) and 'out of lock'
status (DCDB =1). The frequency of pulses is 8 times greater for
'out of lock' than for 'lock'. The LED 'on' indicates power-up whilst
the frequency of pulsing denotes locking status.
Since the display LED is on for (at most) 3.2 % of the total time, the
HBT requires little power which may be further reduced by
employing high efficiency LEDs.
Powered-up, but not locked
Frequency (Hz):
Duration (s):
On time (%):
With 10MHz XTAL :
Powered-up and locked
Frequency (Hz):
Duration (s):
On time (%):
With 10MHz XTAL :
The HBT pin is active High and can supply up to 16mA at a voltage
of > VDD - 0.5 Volts. The display LED should be placed between
the HBT pin and GND with a series resistor. The resistor value is a
function of the efficiency of the display LED, and the power budget.
Example: Calculating the HBT resistor value
LED on voltage:
VDD (ACS104A):
Resistor voltage:
Current to LED:
Resistor value:
Average current:
Average power:
Note: The LED referred to in this section is of the inexpensive
display type and should not be confused with the LED that
interfaces with the fiber optic cable itself.
The power consumption of the ACS104A is a function of the
following:
i.
ii.
iii.
iv.
v.
The sample-clock
The sample-clock selected by DR(1:3), see section headed Data-
Rate Selection, determines the quantity of data transmitted over
the fiber link. The 'transmit' window opens once each frame and
closes when the time compress FIFO is empty.
window is aligned with the 'transmit' window of the far-end modem,
and tracks the 'transmit' window such that it closes on detection of
the last data bit. Clearly, the lower the sample-clock the smaller
the active time and the lower the power consumption.
The transmit current setting
The formula given in section headed LED current control, relates to
the peak current delivered to the LED.
HBT Status pin ('Heartbeat' Indicator LED)
Power consumption considerations
The sample-clock DR(1:3)
The transmit current setting (TRC)
Handshake signals frequency
XTAL frequency
Supply voltage
Frequency:
Frequency:
XTAL / 3.89 * 10
61,440 / XTAL
3.2 % of time.
Duration:
XTAL / 15.36 * 10
61,440 / XTAL
0.4 % of time.
Duration:
0.32mW
2.0V
5.0V
3.0V
2 mA (high efficiency LED)
3/2*10
64µA
ACS104A Data Sheet
-3
= 1500
6
6
2.5Hz (approx.)
6.1ms (approx.)
0.65Hz (approx.)
6.1ms (approx.)
The average current
The 'receive'