S2052 AMCC (Applied Micro Circuits Corp), S2052 Datasheet - Page 4

• Manufacturer Part Number: S2052
• Description: Bicmos Pecl Clock Generator Fibre Channel And Gigabit Ethernet Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Serial/Parallel Conversion
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if
the clock to be recovered is within 100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters. Data is clocked out on the rising edge of RBC1
and RBC0. The parallel data out is 10 bits wide. The
word clock (RBC1) is synchronized to the incoming
data stream word boundary by the detection of the
Fibre Channel Comma character, positive disparity
(0011111XXXX), found in the K28.5 control character.
Transmit Byte Clock Input
The transmit byte clock input must be supplied with a
TTL clock source at 100 PPM tolerance.
Framing
The S2052 provides COM_DET character recognition
and data word alignment of the TTL compatible output
data bus. In systems where the COM_DET function is
undesired, a LOW on the EN_CDET input disables the
COM_DET function and the data will be “un-framed”.
When framing is disabled by low EN_CDET, the S2052
simply achieves bit synchronization within 250 bit times
and begins to deliver parallel output data words when-
ever it has received full transmission words. No attempt
is made to synchronize on any particular incoming char-
acter.
The COM_DET output signal will go high whenever a
positive disparity comma character, found in the K28.5
control character, is present on the parallel data out-
puts. The COM_DET output signal will be low at all
other times.
4
S2052
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Lock Detect
The S2052 lock detect function monitors the state of
the receiver phase-locked loop (PLL) clock recovery
unit. The PLL will lock within 250 bit times after the
start of receiving serial data inputs. If the serial data
inputs have an instantaneous phase jump (from a se-
rial switch, for example) the PLL will not indicate an
out-of-lock state, but will recover the correct phase align-
ment within 50 to 250 bit times, depending on the input
eye opening. (See Fig. 14). If a run length of 80-160
bits is exceeded, or if the input data rate varies by
more than 1000 ppm compared to the reference clock,
the loop will be declared out of lock. When lock is lost,
the PLL will shift from the serial input data to the refer-
ence clock, so that the downstream clock will maintain
the correct frequency.
In any transfer of PLL control from the serial data to the
reference clock, the RBC1/RBC0 output remains phase
continuous and glitch free, assuring the integrity of down-
stream clocking.
OTHER OPERATING MODES
Loopback
When local loopback is enabled, serial data from the
transmitter is internally routed to the receiver, where
the clock is extracted and the data is deserialized. The
parallel data is then sent to the subsystem for verifica-
tion. This loopback mode provides the capability to
perform offline testing of the interface to guarantee the
integrity of the serial channel before enabling the trans-
mission medium. It also allows system diagnostics.
Operating Frequency Range
The S2052 is optimized for operation at 1250 and
1062 Mbit/s. Operation at other rates is possible if the
rate falls between the nominal rates. REFCLK must
be selected to be within 100 ppm of the desired byte
or word clock rate.
April 29, 1999 / Revision E