IDT1028S12Y Integrated Device Technology, Inc., IDT1028S12Y Datasheet - Page 6

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IDT1028S12Y

Manufacturer Part Number
IDT1028S12Y
Description
256K X 4 Static RAM Corner PWR & GND Pinout
Manufacturer
Integrated Device Technology, Inc.
Datasheet
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
ADDRESS
IDT71028 CMOS Static RAM
1 Meg (256K x 4-Bit)
DATA
on the bus for the required t
ADDRESS
DATA
DATA
OUT
WE
CS
IN
WE
CS
IN
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t
t
(3)
AS
t
AS
t
WHZ
(6)
t
AW
t
AW
WP
must be greater than or equal to t
t
WP
t
WC
t
t
6.42
CW
WC
HIGH IMPEDANCE
(2)
6
CS
WE
t
DATA
DW
t
DW
DATA
IN
Commercial and Industrial Temperature Ranges
VALID
WHZ
IN
+ t
VALID
DW
t
DH
t
t
to allow the I/O drivers to turn off and data to be placed
OW
WR
t
WR
(5)
t
DH
t
(3)
CHZ
(5)
2966 drw 08
2966 drw 07
WP
.

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