S3091 AMCC (Applied Micro Circuits Corp), S3091 Datasheet - Page 7

• Manufacturer Part Number: S3091
• Description: Sonet/sdh/atm OC-192 16:1 Transmitter
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3091 – SONET/SDH/ATM OC-192 16:1
Transmitter
S3091 ARCHITECTURE/FUNCTIONAL
DESIGN
MUX OPERATION
The S3091 performs serialization in the processing of
a transmit SONET STS-192 bit serial data stream. It
converts the 16-bit parallel 622.08 Mbps data stream
to bit serial format at 9.953 Gbps.
A high-frequency bit clock is generated from a 155.52
or 622.08 MHz (or equivalent FEC or DW rates) fre-
quency reference by using a frequency synthesizer
that consist of an on-chip phase-lock loop circuit with a
divider, VCO and loop filter.
Clock Divider and Phase Detector
The clock divider and phase detector, shown in the
block diagram in Figure 4, contains monolithic PLL
components that generate signals required to drive the
loop filter. See Table 2 for REFCLK required.
In order for the VCO clock frequency to meet the accu-
racy required for operation in a SONET system, the
REFCLK input must be generated from a differential
ECL crystal oscillator in which the frequency accuracy
equals the value stated in Table 10.
Oscillator phase noise allowable can be defined best by
looking at plots of oscillators that allow the part to meet
SONET jitter generation specifications of 100 mUIpp.
As can be seen from Figures 16 and 17, two different
vendors’ oscillators can yield similar results. For 622
MHz REFCLK, the 82 mUIpp graph is at the noise
floor of the part.
Table 2. FEC Modes
0 bytes per 255-byte block
3 bytes per 255-byte block
4 bytes per 255-byte block
5 bytes per 255-byte block
6 bytes per 255-byte block
7 bytes per 255-byte block
8 bytes per 255-byte block
Digital Wrapper (OTU2)
Error Correcting
Capability
Bandwidth Expansion due
to code words and FSB
Code Rate showing
2.82% Increase
3.66% Increase
4.51% Increase
5.37% Increase
6.25% Increase
7.14% Increase
7.59% Increase
0% Increase
Increased TSD Frequency
For best jitter generation, use a 622.08 MHz oscillator
with a phase noise that meets or exceeds the phase
noise plots shown in Figure 16, or a 155.52 MHz oscil-
lator with a phase noise that meets or exceeds the
phase noise plots in Figure 17.
Timing Generator
The timing generator function, shown in Figure 4, pro-
vides two separate functions. It provides a 16-bit
parallel rate clock and a mechanism for aligning the
phase between the incoming clock and the clock that
loads the parallel-to-serial shift register.
The PCLK output is a 16-bit parallel rate clock. For
STS-192, the PCLK frequency is 622.08 MHz. PCLK
is intended for use as a 16-bit parallel speed clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3091 device.
In the parallel-to-serial conversion process, the incom-
ing data is passed from the PICLK clock timing domain
to the internally generated byte clock timing domain
using an internal FIFO.
The timing generator also produces a feedback refer-
ence clock to the clock synthesizer. A counter divides
the synthesized clock down to the same frequency as
the reference clock (REFCLK). The PLL in the clock
synthesizer maintains the stability of the synthesized
clock by comparing the phase of the feedback clock to
that of the reference clock (REFCLK). The modulus of
the counter is a function of the reference clock fre-
quency and the operating frequency.
10.234 Gbps
10.317 Gbps
10.402 Gbps
10.488 Gbps
10.575 Gbps
10.664 Gbps
10.709 Gbps
9.953 Gbps
Revision A – February 22, 2002
DEVICE SPECIFICATION
Increased Input Clock
(REFCLK) Frequency
669.33 MHz
622.08 MHz
639.62 MHz
644.84 MHz
650.13 MHz
655.48 MHz
660.96 MHz
666.51 MHz
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