S3064 AMCC (Applied Micro Circuits Corp), S3064 Datasheet - Page 4

• Manufacturer Part Number: S3064
• Description: Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Receiver Sonet/sdh/atm Oc-48 Differential 1:16 Receiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3083 ARCHITECTURE/FUNCTIONAL
DESIGN
MUX OPERATION
The S3083 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the byte serial 155.52 Mbyte/sec
data stream to bit serial format at 2.488 Gbps. Diag-
nostic loopback is provided (transmitter to receiver),
and Line Loopback is also provided (receiver to trans-
mitter).
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip phase-
locked loop circuit with a divider, VCO and loop filter.
Clock Divider and Phase Detector
The Clock Divider and Phase Detector, shown in the
block diagram in Figure 4, contains monolithic PLL
components that generate signals required to drive
the loop filter.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a fre-
quency accuracy of better than the value stated in
Table 7 in order for the VCOCLK frequency to have
the same accuracy required for operation in a
SONET system.
In order to meet the 0.01 UI SONET jitter specifica-
tions, the maximum reference clock jitter must be
guaranteed over the 12 kHz to 20 MHz bandwidth.
For details of reference clock jitter requirements, see
Table 2.
The on–chip phase detector, which compares the
phase relationship between the VCO input and the
REFCLK input, drives the loop filter.
Table 2. Reference Jitter Limits
4
S3083
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Timing Generator
The Timing Generator function, seen in Figure 4, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
The PCLK output is a byte rate version of TSCLK.
For STS-48, the PCLK frequency is 155.52 MHz.
PCLK is intended for use as a byte speed clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3083 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to the TSCLK.
The Timing Generator also produces a feedback ref-
erence clock to the Phase Detector. A counter divides
the synthesized clock down to the same frequency
as the reference clock REFCLK.
Parallel-to-Serial Converter
The Parallel-to-Serial converter shown in Figure 4 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PIN[15:0]
bus on the rising edge of PICLK. The parallel-to-
serial register is a loadable shift register which takes
its parallel input from the FIFO output.
An internally generated divide by 16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.
August 27, 1999 / Revision B