S3059 AMCC (Applied Micro Circuits Corp), S3059 Datasheet
S3059
Available stocks
Related parts for S3059
S3059 Summary of contents
Page 1
... SONET-based WDM applications. Figure 1 shows a typical network application. On-chip clock synthesis is performed by the high- frequency Phase Locked Loop (PLL) on the S3059 transceiver chip allowing the use of a slower external transmit clock reference. The chip can be used with a 155.52 MHz reference clock in support of existing system clocking schemes ...
Page 2
... The S3059 is divided into a transmitter section and a receiver section. The sequence of operations is as follows: Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Serial input 2. Serial-to-parallel conversion 3. 16-bit parallel output Internal clocking and control functions are transpar- ent to the user ...
Page 3
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Figure 2. S3059 Transceiver Functional Block Diagram PHINITP/N 2 RATESEL[1:0] CLOCK SYNTHESIZER REFCLKP/N POCLK (Internal) RLPTIME CAP1 CAP2 TESTEN SLPTIME BYPASS 16 PINP/N[15:0] PICLKP/N BYPASSCLKP/N LLEB KILLRXCLK D RSDP/N TXDP/N D (Internal) RSCLKP/N TXCLKP/N (Internal) DLEB SQUELCH SDLVTTL SDLVPECL RSTB October 31, 2000 / Revision B ...
Page 4
... Using PCLK for upstream circuits will ensure a stable fre- quency and phase relationship between the data coming into and leaving the S3059 device. The timing generator also produces a feedback ref- erence clock to the clock synthesizer. A counter divides the synthesized clock down to the same fre- quency as the REFCLK ...
Page 5
... PHERR will go inactive when the realignment is complete. RECEIVER OPERATION The S3059 receiver chip provides the first stage of the digital processing of a receive SONET STS-48/ STS-24/STS-12/STS-3/GBE bit-serial stream. It con- verts the bit-serial 2.488 Gbps, 1.244 Gbps, 622.08 Mbps, 155 ...
Page 6
... For operation with an optical transceiver that pro- vides the “squelched clock” behavior as described above, the S3059 can be operated in the “squelched clock” mode by activating the SQUELCH pin. In this condition, the RSCLKP/N is used for all re- ceiver timing when the SDLVPECL/SDLVTTL inputs are in the active state ...
Page 7
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 4. S3059 Transmitter Pin Assignment and Descriptions ...
Page 8
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 4. S3059 Transmitter Pin Assignment and Descriptions (Continued ...
Page 9
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 5. S3059 Receiver Pin Assignment and Descriptions ...
Page 10
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 5. S3059 Receiver Pin Assignment and Descriptions (Continued ...
Page 11
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 6. S3059 Common Pin Assignment and Descriptions ...
Page 12
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 6. S3059 Common Pin Assignment and Descriptions (Continued ...
Page 13
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 6. S3059 Common Pin Assignment and Descriptions (Continued ...
Page 14
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Figure 3. S3059 Pinout (Top View ...
Page 15
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Figure 4. S3059 Pinout (Bottom View ...
Page 16
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Figure 5. 218 TBGA Package Table 7. Thermal Management ˚ ˚ October 31, 2000 / Revision B ...
Page 17
... S3059 ...
Page 18
... Electrostatic Discharge (ESD) Ratings The S3059 is rated to the following voltages based on the human body model: 1. All pins are rated 100 Volts except pin # V7(CAP1), W7(CAP2), N17(RSCLKN), P17(RSCLKP), R2(REFCLKN), R3(REFCLKP), M2(BYPASSCLKN), N2(BYPASSCLKP), M17(RSDP), and L17(RSDN). Adherence to standards for ESD protection should be taken during the handling of the devices to ensure that the devices are not damaged. The standards to be used are defined in ANSI standard ANSI/ESD S20.20-1999, " ...
Page 19
... V – – – S3059 ...
Page 20
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 14. Single-Ended LVPECL Input DC Characteristics ...
Page 21
... S3059 ...
Page 22
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Table 18. Transmitter AC Timing Characteristics ...
Page 23
... RSD RSD tS POUT POUT S3059 ...
Page 24
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Figure 10. Differential Voltage Measurement V(+) V(–) V(+) – V(-) 0.0V Note: V(+) – V(-) is the algebraic difference of the input signals. 1 Figure 11. Phase Adjust Timing PHERR PHINIT PCLKP PICLKP TRANSFER CLK (Internal) 1. Byte clock = 155.52 MHz SWING SWING ...
Page 25
... MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Figure 12. S3056 to S3059 Differential CML Input Termination +3.3 V S3056 SERDATOP/N SERCLKOP/N Figure 13. +5V Differential CML Driver to S3059 Differential CML Input AC Coupled Termination +5 V S3040/S3050 SERDATOP/N SERCLKOP/N Figure 14. Differential CML Output to +5V PECL Input AC Coupled Termination +3.3 V S3059 TSDP/N TSCLKP/N October 31, 2000 / Revision B Vcc -0 ...
Page 26
... Figure 15. Differential CML Output to +3.3 V PECL Input DC Coupled Termination +3.3 V S3059 TSDP/N TSCLKP/N Figure 16. S3059 Differential LVPECL Driver to Differential LVPECL Input Termination +3.3 V S3059 PCLKP/N, POUTP/N[15:0] POCLKP/N, 155MCKP/N PHERRP/N Figure 17. S3059 Differential LVPECL Driver to Differential LVPECL Input Termination +3.3 V S3059 PCLKP/N, POUTP/N[15:0] POCLKP/N, 155MCKP/N PHERRP/N 26 +3.3 V Zo=50 100 Zo=50 +3 ...
Page 27
... Figure 18. S3059 Differential LVPECL Driver to Differential LVPECL Input Termination +3.3 V S3059 PCLKP/N, POUTP/N[15:0] POCLKP/N, 155MCKP/N PHERRP/N 1. With 100 line-to-line, V Max increases by 100 Figure 19. Differential LVPECL Driver to S3059 Internally Biased Differential LVPECL Inputs +3.3V Figure 20. External Loop Filter Components October 31, 2000 / Revision B Zo=50 200 200 Zo=50 Zo=50 100 ...
Page 28
... S3059 MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER Ordering Information – Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...