S3057 AMCC (Applied Micro Circuits Corp), S3057 Datasheet

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S3057

Manufacturer Part Number
S3057
Description
Bicmos Lvpecl Clock Generator Sonet/sdh/atm Oc-12 Transmitter And Receiver Multirate (oc-48/24/12/3/gbe) Sonet/sdh/atm Transceiver
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet
1.S3057.pdf (22 pages)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
S3057TB
Manufacturer:
amcc
Quantity:
1 831
FEATURES
APPLICATIONS
Figure 1. System Block Diagram
DEVICE
SPECIFICATION
December 6, 1999 / Revision NC
SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER
SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER
• Micro-power Bipolar supply
• Complies with Bellcore, and ITU-T
• On-chip high-frequency PLL for clock
• Supports 2.488 Gbps (OC-48)
• Reference frequency of 155.52 MHz
• Interface to both LVPECL and LVTTL logic
• 16-bit Differential LVPECL data path
• Compact 100 TQFP/TEP package
• Diagnostic loopback mode
• Line loopback mode
• Lock detect
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3V supply
• Typical power 1.45 W
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• DWDM Systems
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
specifications
generation
16
16
S3063
S3064
Tx
Rx
S3056
OTX
ORX
ORX
GENERAL DESCRIPTION
The S3063 SONET/SDH MUX chip is a fully integrated
serialization SONET OC-48 (2.488 Gbps) interface de-
vice. The chip performs all necessary parallel-to-serial
functions in conformance with SONET/SDH transmis-
sion standards. The device is suitable for SONET-
based ATM applications. Figure 1 shows a typical
network application.
On-chip clock synthesis PLL components are con-
tained in the S3063 MUX chip allowing the use of a
slower external transmit clock reference. The chip
can be used with a 155.52 MHz reference clock, in
support of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3063 is pack-
aged in a 100 TQFP/TEP, offering designers a small
package outline.
OTX
S3056
S3064
S3063
Rx
Tx
16
16
S3063
S3063
®
1

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S3057 Summary of contents

Page 1

DEVICE SPECIFICATION SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER FEATURES • Micro-power Bipolar supply • Complies with Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation • Supports 2.488 Gbps (OC-48) • Reference frequency of ...

Page 2

S3063 SONET OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the opti- cal level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for ...

Page 3

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER S3063 OVERVIEW The S3063 transmitter implements SONET/SDH se- rialization and transmission functions. The block dia- gram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front ...

Page 4

S3063 S3063 ARCHITECTURE/FUNCTIONAL DESIGN MUX OPERATION The S3063 performs the serializing stage in the pro- cessing of a transmit SONET STS-48 bit serial data stream. It converts the 16-bit serial 155.52 Mbyte/sec data stream to bit serial format at 2.488 ...

Page 5

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER FIFO Initialization The FIFO can be initialized in one of the following three ways: 1. During power up, once the PLL has locked to the reference clock provided on the REFCLK pins, the LOCKDET will ...

Page 6

S3063 Table 3. Input Pin Assignment and Descriptions ...

Page 7

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Table 3. Input Pin Assignment and Descriptions (Continued ...

Page 8

S3063 Table 4. Output Pin Assignment and Descriptions ...

Page 9

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Table 5. Common Pin Assignment and Description ...

Page 10

S3063 Figure 5. S3063 Pinout 100 TQFP/TEP LSCLKP 1 LSCLKN 2 CORE_VCC 3 CORE_GND 4 5 LSDP LSDN 6 RSTB 7 8 LVP_GND LLCLKP 9 10 LLCLKN 11 LVP_VCC LLDP 12 13 LLDN 14 LVP_VCC 15 LVP_GND 16 TTL_GND 155MCKP ...

Page 11

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Figure 6. 100 TQFP/TEP Package TOP VIEW Note: The S3063 pacakge is equipped with an embedded conductive heatsink on the top. Table 6. Thermal Management Add 45 mA for ...

Page 12

S3063 Table 7. Performance Specifications ...

Page 13

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Table 10. Absolute Maximum Ratings ...

Page 14

S3063 Table 13. LVTTL Input/Output DC Characteristics ...

Page 15

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Table 16. Internally Biased Differential LVPECL Input DC Characteristics ...

Page 16

S3063 Figure 7. Line Loopback Input Timing Diagram LLCLKP LLDP/N Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input. Table 20. AC Transmitter Timing ...

Page 17

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Figure 8. AC Input Timing PICLKP PINP/N[15:0] 1. When a set-up time is specified on LVPECL signals between an input and a clock, the set-up time is the time in nanoseconds from the crossover point ...

Page 18

S3063 Figure 11. Phase Adjust Timing PHERR PHINIT PCLK PICLK TRANSFER CLK (Internal) 1. Byte Clock = 155.52 MHz. 18 SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER 4-10 BYTE CLOCKS 1 2 BYTE CLOCKS 1 December 6, 1999 / Revision NC ...

Page 19

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Figure 12. External Loop Filter Figure 13. Differential CML Output to +5V PECL Input AC Coupled Termination +3.3V S3063 TSDP/N TSCLKP/N Figure 14. +5V Differential PECL Driver to S3063 Differential LVPECL Input AC Coupled Termination ...

Page 20

S3063 Figure 15. S3063 to Differential LVPECL Input S3063 Terminations +3.3V S3063 PCLKP/N PHERRP/N Figure 16. S3063 to S3064 for Diagnostic Loopback +3.3V S3063 LSDP/N LSCLKP/N F igure 17. Differential LVPECL Driver to S3063 Internally Biased Differential LVPECL Input AC ...

Page 21

SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER Figure 19. Differential LVPECL Driver to Differential LVPECL Input PINP/N[15:0] Vcc Differential Driver December 6, 1999 / Revision NC Zo=50 100 150 150 Zo=50 PINP/N[15:0] S3063 +3.3V S3063 21 ...

Page 22

S3063 Ordering Information – Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) ...

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