S3055 AMCC (Applied Micro Circuits Corp), S3055 Datasheet - Page 4

• Manufacturer Part Number: S3055
• Description: Sonet/sdh/atm OC-48 16 Bit Transceiver With CDR
• Manufacturer: AMCC (Applied Micro Circuits Corp)

4
S3055 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3055 transceiver chip performs the serializa-
tion stage in the processing of a transmit SONET
STS-48 data stream. It converts 16-bit parallel data
to bit serial format at 2488.32 Mbps.
A high-frequency bit clock can be generated from a
155.52 MHz frequency reference by using an inte-
gral frequency synthesizer consisting of a
Phase-Locked Loop (PLL) circuit with a divider in
the loop.
Diagnostic loopback (transmitter to receiver) and
line loopback (receiver to transmitter) is provided.
See Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram
in Figure 2, is a monolithic PLL that generates the
serial output clock frequency locked to the input Ref-
erence Clock (REFCLKP/N).
The REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy
that meets the value stated in Table 7, the frequency
spectrum in Figure 11. In order for the Transmit Se-
rial Clock (TSCLK) frequency to have the same
accuracy required for operation in a SONET system.
The REFCLK must meet the phase noise require-
ments shown in Figure 11 to meet the jitter
generation specifications given in Table 7. Lower ac-
curacy crystal oscillators may be used in
applications less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The timing generation function, seen in Figure 2,
provides a divide-by-16 rate version of the transmit
serial clock. This circuitry also provides an internally gen-
erated load signal, which transfers the PINP/N[15:0]
data from the FIFO to the serial shift register.
The PCLK output is a divide-by-16 rate version of
the transmit serial clock. PCLK is intended for use as
a divide-by-16 clock for upstream multiplexing and
overhead processing circuits. Using PCLK for up-
stream circuits will ensure a stable frequency and
phase relationship between the data coming into and
leaving the S3055 device.
The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the REFCLK. The PLL in the clock
synthesizer maintains the stability of the synthesized
clock by comparing the phase of the internal clock
with that of the REFCLK.
Table 2. Reference Jitter Limits
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