S3042 AMCC (Applied Micro Circuits Corp), S3042 Datasheet - Page 4

• Manufacturer Part Number: S3042
• Description: Sonet/sdh/atm OC-48 1:8 Receiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3043 ARCHITECTURE/FUNCTIONAL
DESIGN
MUX OPERATION
The S3043 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the byte serial 155.52 Mbyte/sec
data stream to bit serial format at 2.488 Gbps. Diag-
nostic loopback is provided (transmitter to receiver),
and Line Loopback is also provided (receiver to trans-
mitter).
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip phase-
locked loop circuit with a divider, VCO and loop filter.
Clock Divider and Phase Detector
The clock divider and phase detector, shown in the
block diagram in Figure 4, contains monolithic PLL
components that generate signals required to drive
the loop filter.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a fre-
quency accuracy of better than 20 ppm in order for
the VCOCLK frequency to have the same accuracy
required for operation in a SONET system.
In order to meet the 0.01 UI SONET jitter specifica-
tions, the maximum reference clock jitter must be
guaranteed over the 12 kHz to 20 MHz bandwidth.
For details of reference clock jitter requirements, see
Table 2.
The on–chip phase detector, which compares the
phase relationship between the VCO input and the
REFCLK input, drives the loop filter.
Timing Generator
The timing generator function, seen in Figure 4, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
Table 2. Reference Jitter Limits
4
S3043
M
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2
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B
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J
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t t i
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t a
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4 -
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g
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
The PCLK output is a byte rate version of TSCLK.
For STS-48, the PCLK frequency is 155.52 MHz.
PCLK is intended for use as a byte speed clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3043 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to TSCLK.
The timing generator also produces a feedback ref-
erence clock to the Phase Detector. A counter divides
the synthesized clock down to the same frequency
as the reference clock REFCLK.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first register
latches the data from the PIN[15:0] bus on the rising
edge of PICLK. The second register is a parallel
loadable shift register which takes its parallel input
from the first register.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in the
Timing Generator description, activates the parallel
data transfer between registers. The serial data is
shifted out of the second register at the TSCLK rate.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output data
from the transmitter is routed to the receiver in place
of the normal data stream (RSD).
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3043, it selects the
source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable
(LLEB) input is active, it selects data and clock from
the Parallel to Serial Converter block. When LLEB is
inactive, it forces the output data multiplexer to se-
lect data and clock from the LLD and LLCLK inputs,
and a receive-to-transmit loopback can be estab-
lished at the serial data rate.
August 10, 1999 / Revision E