FR65E Fujitsu Microelectronics, Inc., FR65E Datasheet - Page 17

• Manufacturer Part Number: FR65E
• Description: 32-bit Microcontroller
• Manufacturer: Fujitsu Microelectronics, Inc.

• Notes on the PS register
• Notes on
• Simultaneous occurrences of a software break and a user interrupt/NMI
• Single-stepping the RETI instruction
• A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to
access to the area containing the address of a system stack pointer.
Unique to the evaluation chip MB91V307R
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the
microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs
operations before and after the EIT as specified in either case.
Do not access data in the instruction cache control register or the instruction cache RAM immediately before
the RETI instruction.
When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause
the following phenomena:
If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has
been used, avoid setting any break at the relevant location.
If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being
executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
The debugger stops pointing to a location other than the programmed breakpoints.
The halted program is not re-executed correctly.
The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as that in (1) above.
updated to the same values as those in (1) above.
I-BUS
Memory
MB91307B
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