S1D13A05 Epson Electronics America, Inc., S1D13A05 Datasheet
S1D13A05
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S1D13A05 Summary of contents
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... S1D13A05 LCD/USB Companion Chip S1D13A05 TECHNICAL MANUAL Document Number: X40A-Q-001-01 Copyright © 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13A05 X40A-Q-001-01 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 02/01/22 ...
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... Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/ S1D13A05 X40A-Q-001-01 ...
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... Page 4 S1D13A05 X40A-Q-001-01 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 02/01/22 ...
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... The S1D13A05 integrates a USB slave controller and an LCD graphics controller with an embedded 256K byte SRAM display buffer. The LCD controller supports all standard panel types and multiple TFT types eliminating the need for an external timing control IC. The S1D13A05 includes a Hardware Acceleration Engine to greatly improve screen drawing functions and the built-in USB controller provides revision 1 ...
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... USBCLK. Package • 121-pin PFBGA • 128-pin QFP5 CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS • S1D13A05 Technical • Palm OS Manual • S5U13A05 Evaluation Boards • Windows • CPU Independent Software • VXWorks Utilities Japan ...
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... S1D13A05 LCD/USB Companion Chip Hardware Functional Specification Document Number: X40A-A-001-06 Status: Revision 6.01 Issue Date: 2005/05/19 © SEIKO EPSON CORPORATION 2002 - 2005. Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13A05 X40A-A-001-06 Epson Research and Development Hardware Functional Specification Revision 6.01 Vancouver Design Center Issue Date: 2005/05/19 ...
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... Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 28 4.4 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.1 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Hardware Functional Specification Issue Date: 2005/05/19 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision 6.01 Page 3 S1D13A05 X40A-A-001-06 ...
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... USB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.1 Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.1.1 BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.1.2 MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.1.3 PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.1.4 PWMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.3 Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8.1 Register Mapping 8.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 8.3 LCD Register Descriptions (Offset = 0h .98 S1D13A05 X40A-A-001- .95 Revision 6.01 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2005/05/19 ...
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... SwivelView 90° 180 14.2.2 SwivelView 180° 180 14.2.3 SwivelView 270° 181 15 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16 USB Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.1 USB Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Hardware Functional Specification Issue Date: 2005/05/ 167 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 . . . . . . . . . . . . . . . . . . . . . . . . . 180 Revision 6. 158 X40A-A-001-06 Page 5 S1D13A05 ...
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... Page 6 19 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 S1D13A05 X40A-A-001-06 Epson Research and Development Hardware Functional Specification Revision 6.01 Vancouver Design Center Issue Date: 2005/05/19 ...
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... The S1D13A05 also provides support for “Picture-in-Picture Plus” (a variable size Overlay window). The S1D13A05, with its integrated USB client, provides impressive support for Palm OS handhelds. However, its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. ...
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... Extended TFT interfaces (Type • ‘Direct’ support for 18-bit Sharp HR-TFT LCD (or compatible interfaces). • ‘Direct’ support for the Casio TFT LCD (or compatible interfaces). S1D13A05 X40A-A-001-06 Epson Research and Development Hardware Functional Specification Revision 6 ...
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... Single clock input possible if USB support not required. 2.7 USB Device • USB Client, revision 1.1 compliant. • Dedicated clock input: USBCLK. • 48MHz crystal oscillator for USBCLK. Hardware Functional Specification Issue Date: 2005/05/ displays a variable size window overlaid over back- Revision 6.01 Page 9 S1D13A05 X40A-A-001-06 ...
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... General Purpose Input/Output pins are available. • IO Operates at 3.3 volts ± 10%. • Core operates at 2.0 volts ± 10% or 2.5 volts ± 10%. • 121-pin PFBGA package. • 128-pin QFP5 package. S1D13A05 X40A-A-001-06 Epson Research and Development Transparent Write BitBLT Transparent Move BitBLT Read BitBLT ...
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... RESET# . Oscillator BS# RD/WR# M/R# CS# AB[17:0] DB[15:0] S1D13A05 WE0# WE1# RD# WAIT# CLKI RESET# Revision 6.01 Page 11 16-bit Single FPDAT[15:0] D[15:0] LCD FPFRAME FPFRAME Display FPLINE FPLINE FPSHIFT FPSHIFT DRDY MOD GPIO0 9-bit FPDAT[8:0] D[8:0] TFT FPFRAME FPFRAME Display FPLINE FPLINE FPSHIFT FPSHIFT DRDY DRDY GPIO0 S1D13A05 X40A-A-001-06 ...
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... Oscillator AB0 M/R# CS# AB[17:1] DB[15:0] WE0# WE1# S1D13A05 BS# RD/WR# RD# WAIT# CLKI RESET# . Oscillator AB0 M/R# CS# AB[17:1] DB[15:0] WE0# WE1# S1D13A05 BS# RD/WR# RD# WAIT# CLKI RESET# Revision 6.01 Epson Research and Development Vancouver Design Center 12-bit FPDAT15 D11 TFT FPDAT12 D10 Display FPDAT[9:0] D[9:0] FPFRAME FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY ...
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... WE0# WAIT# CLKI RESET# Revision 6.01 Page 13 FPDAT[17:0] D[17:0] 18-bit SPS FPFRAME HR-TFT FPLINE LP Display FPSHIFT CLK GPIO0 PS CLS GPIO1 GPIO2 REV GPIO3 SPL FPDAT[17:0] D[17:0] 18-bit SPS FPFRAME HR-TFT FPLINE LP Display FPSHIFT CLK GPIO0 PS GPIO1 CLS GPIO2 REV GPIO3 SPL S1D13A05 X40A-A-001-06 ...
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... S1D13A05 X40A-A-001-06 . Oscillator BS# M/R# CS# AB[17:1] DB[15:0] S1D13A05 RD/WR# RD# WE0# WE1# CLKI RESET# AB0 . Oscillator BS# RD/WR# M/R# CS# AB[17:1] DB[15:0] S1D13A05 WE0# WE1# RD# WAIT# CLKI RESET# AB0 Revision 6.01 Epson Research and Development Vancouver Design Center 4-bit Single FPDAT[7:4] D[3:0] LCD FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD ...
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... USBDM (GPIO6) VSS Hardware Functional Specification Issue Date: 2005/05/19 150kΩ 300kΩ Full Speed Device IOVDD 1.5kΩ 20Ω 20Ω 300kΩ NNCD5.6LG Overvoltage Protection ESD Protection Figure 3-9: USB Typical Implementation Revision 6.01 Page 15 USB Socket VBus DP DM GND S1D13A05 X40A-A-001-06 ...
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... VSS RD/WR# E RD# BS# M/R# D AB0 AB1 AB2 C USBOSCO COREVDD AB3 B USBOSCI VSS AB5 A NC COREVDD AB4 1 2 S1D13A05 X40A-A-001- BOTTOM VIEW Table 4-1: PFBGA 121-pin Mapping DB3 DB0 GPIO7 DB4 DB1 GPIO6 DB5 DB2 GPO3 DB13 GPO2 IOVDD ...
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... Issue Date: 2005/05/19 S1D13A05 Figure 4-2: Pinout Diagram - QFP5 128-pin Revision 6.01 Page 17 GPO8 64 FPDAT17 63 CNF6 62 FPDAT16 61 FPDAT14 60 FPDAT15 59 TESTEN 58 57 FPDAT9 56 FPDAT10 FPDAT11 55 FPDAT12 54 53 FPDAT8 52 IOVDD 51 FPDAT7 50 VSS 49 FPDAT6 48 FPDAT4 47 FPDAT3 46 FPDAT2 45 FPDAT1 44 FPDAT0 43 FPSHIFT 42 FPLINE 41 GPO5 40 FPFRAME 39 COREVDD S1D13A05 X40A-A-001-06 ...
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... B6,E6,D5, 86,113,87, A5,B5,C5, 90,91,88, AB[17:1] D4,A4,C4, 95,94,92, B3,A3,C3, 96,97,102, D3,D2 104,105 S1D13A05 X40A-A-001-06 LVTTL is Low Voltage TTL. Table 4-2: Host Interface Pin Descriptions I/O type RESET# (see key State above) This input pin has multiple functions. • For Generic #1, this pin is not used and should be connected to VSS. • For Generic #2, this pin inputs system address bit 0 (A0). ...
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... For DragonBall, this pin inputs the byte enable signal for the D[15:8] data byte (UWE). ⎯ CI Chip select input. This input pin is used to select between the display buffer and ⎯ LI register address spaces of the S1D13A05. M/R# is set high to access the display buffer and low to access the registers. Revision 6.01 Page 19 Description DD S1D13A05 X40A-A-001-06 ...
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... For Generic #2, this pin must be tied • For SH-3/SH-4, this pin inputs the RD/WR# signal. The ⎯ S1D13A05 needs this signal for early decode of the bus LI cycle. • For MC68K #1, this pin inputs the R/W# signal. • For MC68K #2, this pin inputs the R/W# signal. ...
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... If CNF5 = 0, the WAIT# pin should be tied high using a pull-up resistor. If WAIT# is not used, this pin should be tied either high or low using a pull-up or pull-down resistor. Active low input to set all internal registers to the default state ⎯ LI and to force all signals to their inactive states. Revision 6.01 Page 21 Description S1D13A05 X40A-A-001-06 ...
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... H10 43 DRDY K9 34 GPO0 K1 14 GPO1 J1 15 GPO2 H5 16 S1D13A05 X40A-A-001-06 Table 4-3: LCD Interface Pin Descriptions I/O type RESET# (see key State above) LB3P 0 Panel Data bits 17-0. This output pin has multiple functions. • Frame Pulse • SPS for HR-TFT LB3P 0 • ...
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... When this pin is used for the above display modes, it must be configured as an output using REG[64h] after every RESET. Otherwise, it defaults to a Hi-Z state after every RESET and must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain. Revision 6.01 Page 23 Description S1D13A05 X40A-A-001-06 ...
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... GPIO1 J7 27 GPIO2 K7 25 GPIO3 L7 26 GPIO4 H7 28 S1D13A05 X40A-A-001-06 Table 4-3: LCD Interface Pin Descriptions I/O type RESET# (see key State above) This pin has multiple functions. • CLS for HR-TFT • GRES for Casio • AP for TFT Type 2 • OE for TFT Type 3 ⎯ ...
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... This output pin is the IRQ pin for USB. When IRQ is activated, an active high pulse is generated and stays high LO3 0 until the IRQ is serviced by software at REG[404Ah] or REG[404Ch]. This pin has multiple functions. LO3 0 • PWM Clock output • General purpose output Revision 6.01 Page 25 Description S1D13A05 X40A-A-001-06 ...
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... F5 118 CLKI2 B9 70 USBCLK J8 32 USBOSCI B1 82 USBOSCO C1 81 S1D13A05 X40A-A-001-06 Table 4-4: Clock Input Pin Descriptions I/O type RESET# (see key State above) Typically used as input clock source for bus clock and memory CI — clock CI — Optionally used as input clock source for pixel clock Used as input clock source for USB ...
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... Issue Date: 2005/05/19 Table 4-5: Miscellaneous Pin Descriptions I/O type (see RESET# key above) State These inputs are used to configure the S1D13A05 - see Table 4-7: “Summary of Power-On/Reset Options,” on page 28. CI — Note: These pins are used for configuration of the S1D13A05 and must be connected directly ...
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... Page 28 4.3 Summary of Configuration Options These pins are used for configuration of the S1D13A05 and must be connected directly to IOV state at any other time has no effect. Table 4-7: Summary of Power-On/Reset Options S1D13A05 Configuration 1 (connected Input Select host bus interface as follows: CNF4 ...
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... WAIT# WAIT# RESET# RESET# RESET# Note 1 A0 for these busses is not used internally by the S1D13A05 and should be connected the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. Hardware Functional Specification Issue Date: 2005/05/19 Table 4-8: Host Bus Interface Pin Mapping ...
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... GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 GPO8 GPO9 GPO10 PWMOUT S1D13A05 X40A-A-001-06 Table 4-9: LCD Interface Pin Mapping Generic TFT (TFT Type 1) Format 2 16-Bit 8-bit 9-bit 12-bit 18-bit FPLINE FPSHIFT MOD DRDY (G3) ...
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... FPDATxx signals at the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see Section 6.4, “Display Interface” on page 56. 3 The S1D13A05 also supports the 9-bit and 12-bit variations of the Type 4 TFT panel. Hardware Functional Specification Issue Date: 2005/05/19 Revision 6.01 ...
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... Page 32 5 D.C. Characteristics Note When applying Supply Voltages to the S1D13A05, Core V chip before, or simultaneously with IO V Symbol Parameter Core V Supply Voltage Supply Voltage DD V Input Voltage IN V Output Voltage OUT T Storage Temperature STG T Solder Temperature/Time SOL Table 5-2: Recommended Operating Conditions ...
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... Hardware Functional Specification Issue Date: 2005/05/19 = 3.3V ± 10% DD for all inputs must be < 5 nsec (10% ~ 90%) fall t t PWH PWL OSC Figure 6-1: Clock Input Requirements Parameter Revision 6.01 Page 33 Min Max Units 100 MHz 1/f ns OSC 4 S1D13A05 X40A-A-001-06 ...
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... Input Clock Rise Time (10% - 90%) r Note Maximum internal requirements for clocks derived from CLKI2 must be considered when determining the frequency of CLKI2. See Section 6.1.2, “Internal Clocks” on page 35 for internal clock requirements. S1D13A05 X40A-A-001-06 Parameter Parameter Revision 6.01 Epson Research and Development ...
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... MCLK is derived from BCLK, therefore when BCLK is greater than 50MHz, MCLK must be divided using REG[04h] bits 5-4. Note For further information on internal clocks, refer to Section 7, “Clocks” on page 90. Hardware Functional Specification Issue Date: 2005/05/19 Table 6-4: Internal Clock Requirements Parameter COREVDD = 2.0V COREVDD = 2.5V Revision 6.01 Page 35 Min Max Units 66 MHz 30 MHz 50 MHz 50 MHz 66 MHz S1D13A05 X40A-A-001-06 ...
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... A[16:1], M/R# and CS# hold from RD0#, RD1#, WE0#, WE1# rising t5 edge t6 CS# deasserted to reasserted t7 WAIT# rising edge to RD0#, RD1#, WE0#, WE1# rising edge t8 WE0#, WE1#, RD0#, RD1# deasserted to reasserted t9 CLK rising edge to WAIT# rising edge S1D13A05 X40A-A-001-06 T CLK t1 t2 t15 t3 t4 t11 valid ...
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... Because A0 is not used internally, all addresses are seen by the S1D13A05 as even addresses (16-bit word address aligned on even byte addresses). Hardware Functional Specification Issue Date: 2005/05/19 Table 6-5: Generic #1 Interface Timing Parameter D[15:8] D[7:0] valid valid 16-bit write ...
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... Page 38 6.2.2 Generic #2 Interface Timing BUSCLK A[16:0], M/R#, BHE# CS# WE#, RD# WAIT# D[15:0] (write) D[15:0] (read) S1D13A05 X40A-A-001-06 T BUSCLK t1 t2 t15 t3 t4 t11 valid Figure 6-3: Generic #2 Interface Timing Revision 6.01 Epson Research and Development Vancouver Design Center t10 t12 t14 t13 valid Hardware Functional Specification ...
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... Revision 6.01 Page 39 Min Max Unit 50 MHz 1/f ns BUSCLK BUSCLK BUSCLK 0 ns 0.5 T BUSCLK BUSCLK Comments S1D13A05 X40A-A-001-06 ...
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... Page 40 6.2.3 Hitachi SH-3 Interface Timing CKIO A[16:1], M/R#, RD/WR# BS# CSn# WEn#, RD# WAIT# D[15:0] (write) D[15:0] (read) Note A minimum of one software wait state is required. S1D13A05 X40A-A-001-06 T CKIO t1 t17 Figure 6-4: Hitachi SH-3 Interface Timing Revision 6.01 Epson Research and Development Vancouver Design Center t8 t9 t10 t11 t13 ...
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... D[15:0] hold from WEn# deasserted (write cycle) t15 D[15:0] setup to WAIT# rising edge (read cycle) t16 Rising edge of RD# to D[15:0] high impedance (read cycle) t17 Cycle Length 1. The S1D13A05 requires 2ns of write data hold time. Hardware Functional Specification Issue Date: 2005/05/19 Table 6-10: Hitachi SH-3 Interface Timing Parameter Revision 6.01 Page 41 ...
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... Page 42 6.2.4 Hitachi SH-4 Interface Timing CKIO A[16:1], RD/WR#, M/R# BS# CSn# WEn#, RD# RDY D[15:0] (write) D[15:0] (read) Note A minimum of one software wait state is required. S1D13A05 X40A-A-001-06 T CKIO t1 t18 Figure 6-5: Hitachi SH-4 Interface Timing Revision 6.01 Epson Research and Development Vancouver Design Center t8 t9 t10 t11 t14 ...
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... Issue Date: 2005/05/19 Table 6-11: Hitachi SH-4 Interface Timing Parameter Revision 6.01 Page 43 Min Max Unit 66 MHz 1/f ns CKIO CKIO 2 T CKIO 0.5 T CKIO CKIO S1D13A05 X40A-A-001-06 ...
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... Page 44 6.2.5 Motorola MC68K #1 Interface Timing T CLK CLK t1 A[16:1], R/W#, M/R# t1 CS# t1 AS# t1 UDS#, LDS#, (A0) DTACK# D[15:0] (write) D[15:0] (read) Figure 6-6: Motorola MC68K #1 Interface Timing S1D13A05 X40A-A-001-06 t13 t10 t11 Revision 6.01 Epson Research and Development Vancouver Design Center t12 Hardware Functional Specification ...
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... UDS#, LDS# rising edge to D[15:0] high impedance (read cycle) t13 Cycle Length Hardware Functional Specification Issue Date: 2005/05/19 Parameter Revision 6.01 Page 45 Min Max Unit 50 MHz 1/f ns CLK 0 CLK CLK 0 ns 0.5 T CLK CLK S1D13A05 X40A-A-001-06 ...
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... Page 46 6.2.6 Motorola MC68K #2 Interface Timing CLK A[16:1], M/R#, R/W#, SIZ[1:0] CS# AS# DS# DSACK1# D[31:16] (write) D[31:16] (read) Figure 6-7: Motorola MC68K #2 Interface Timing S1D13A05 X40A-A-001-06 T CLK t11 t13 valid Revision 6.01 Epson Research and Development Vancouver Design Center t3 t15 t10 t9 t12 valid t14 ...
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... DS# rising edge to D[15:0] high impedance (read cycle) t15 Cycle Length Hardware Functional Specification Issue Date: 2005/05/19 Parameter Revision 6.01 Page 47 Min Max Unit 50 MHz 1/f ns CLK CLK 1 T CLK 0 ns 0.5 T CLK CLK S1D13A05 X40A-A-001-06 ...
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... Page 48 6.2.7 Motorola REDCAP2 Interface Timing T CKO CKO t1 A[16:1], R/W#, CS# t2 EBO#, EB1# (write) D[15:0] (write) t5 EB0#, EB1#, OE# (read) t7 D[15:0] (read) Figure 6-8: Motorola Redcap2 Interface Timing S1D13A05 X40A-A-001-06 t12 t4 t3 valid t6 valid Revision 6.01 Epson Research and Development Vancouver Design Center t8 t9 t10 t11 Hardware Functional Specification ...
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... CKO Revision 6.01 Page 49 Min Max Unit 17 MHz 1/f ns CKO CKO +17 ns CKO 9T +17 ns CKO 12T +17 ns CKO 15T +17 ns CKO CKO S1D13A05 X40A-A-001-06 ...
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... Motorola Dragonball Interface Timing with DTACK CLKO t1 A[16:1] t1 CSX# t1 UWE#, LWE# (write) t1 OE# (read) D[15:0] (write) D[15:0] (read) t2 DTACK# Figure 6-9: Motorola Dragonball Interface Timing with DTACK S1D13A05 X40A-A-001-06 T CLKO t13 Revision 6.01 Epson Research and Development Vancouver Design Center Valid ...
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... The MC68EZ328 with a maximum clock frequency of 16MHz is supported. Hardware Functional Specification Issue Date: 2005/05/19 Parameter Revision 6.01 Page 51 Min Max Unit 66 (note 1) MHz 1/f ns CLKO CLKO 1 T CLKO 0 ns 0.5 T CLKO 0. 0. CLKO CLKO 8 T CLKO S1D13A05 X40A-A-001-06 ...
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... Page 52 6.2.9 Motorola Dragonball Interface Timing w/o DTACK CLKO t1 A[16:1] t1 CSX# t1 UWE#, LWE# (write) t1 OE# D[15:0] (write) t3 D[15:0] (read) Figure 6-10: Motorola Dragonball Interface Timing w/o DTACK S1D13A05 X40A-A-001-06 T CLKO Revision 6.01 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2005/05/19 ...
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... Hardware Functional Specification Issue Date: 2005/05/19 Parameter ÷ 3 and MCLK = BCLK ÷ 4 option. Revision 6.01 Page 53 Min Max Unit 33 (note 1) MHz 1/f ns CLKO CLKO CLKO 10 T CLKO 13 T CLKO CLKO ÷ 4 options. . CLKO S1D13A05 X40A-A-001-06 ...
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... Symbol t1 LCD signals active to LCD bias active t2 Power Save Mode disabled to LCD signals active controlled by software and must be determined from the bias power supply delay requirements of the panel connected. S1D13A05 X40A-A-001- Parameter Revision 6.01 Epson Research and Development Vancouver Design Center ...
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... Power Save Mode enabled to LCD signals low controlled by software and must be determined from the bias power supply delay requirements of the panel connected. Hardware Functional Specification Issue Date: 2005/05/19 t1 Parameter Revision 6.01 Page 55 t2 Min Max Units Note 1 Note BCLK S1D13A05 X40A-A-001-06 ...
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... For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16. For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples The following formulas must be valid for all panel timings: HDPS + HDP < HT VDPS + VDP < VT S1D13A05 X40A-A-001-06 HT HDPS HPS ...
Page 63
... Figure 6-14: Generic STN Panel Timing = [(REG[30h] bits 9- lines = 0 lines, because REG[2Ch] bits 9 [(REG[3Ch] bits 18-16 lines = 0 lines, because REG[38h] bits 9 [(REG[34h] bits 9- lines = [((REG[20h] bits 6- pixels = [(REG[2Ch] bits 9- pixels = [(REG[2Ch] bits 22-16 pixels = [((REG[24h] bits 6- pixels Revision 6.01 Page 57 HPW S1D13A05 X40A-A-001-06 ...
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... Vertical Non-Display Period = VT - VDP = (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines HDP = Horizontal Display Period = ((REG[24h] bits 6: 8Ts HNDP = Horizontal Non-Display Period = HT - HDP = (((REG[20h] bits 6: 8Ts) - (((REG[24h] bits 6: 8Ts) S1D13A05 X40A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP 1-1 ...
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... Revision 6. t14 t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 note 4 note 5 note 6 note t14 + note 8 X40A-A-001-06 Page 59 Units S1D13A05 ...
Page 66
... Vertical Non-Display Period = VT - VDP = (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines HDP = Horizontal Display Period = ((REG[24h] bits 6: 8Ts HNDP = Horizontal Non-Display Period = HT - HDP = (((REG[20h] bits 6: 8Ts) - (((REG[24h] bits 6: 8Ts) S1D13A05 X40A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-1 ...
Page 67
... Revision 6. t14 t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 note 4 note 5 note 6 note t14 + note 8 X40A-A-001-06 Page 61 Units S1D13A05 ...
Page 68
... Vertical Non-Display Period = VT - VDP = (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines HDP = Horizontal Display Period = ((REG[24h] bits 6: 8Ts HNDP = Horizontal Non-Display Period = HT - HDP = (((REG[20h] bits 6: 8Ts) - (((REG[24h] bits 6: 8Ts) S1D13A05 X40A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 HDP .5Ts .5Ts ...
Page 69
... Revision 6. t11 t10 t12 t13 1 2 Min Typ Max Units note 2 Ts (note 1) note 3 Ts note 4 Ts note 5 Ts note 6 Ts note t14 + 0 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts note 8 Ts S1D13A05 X40A-A-001-06 Page 63 ...
Page 70
... Vertical Non-Display Period = VT - VDP = (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines HDP = Horizontal Display Period = ((REG[24h] bits 6: 8Ts HNDP = Horizontal Non-Display Period = HT - HDP = (((REG[20h] bits 6: 8Ts) - (((REG[24h] bits 6: 8Ts) S1D13A05 X40A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 HDP 2Ts 2Ts ...
Page 71
... Revision 6. t11 t10 t12 t13 t12 t13 2 1 Min Typ Max Units note 2 Ts (note 1) note 3 note 4 note 5 note 6 note 7 t6a + t4 t6b + t4 t14 + note 8 S1D13A05 X40A-A-001-06 Page ...
Page 72
... Vertical Non-Display Period = VT - VDP = (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines HDP = Horizontal Display Period = ((REG[24h] bits 6: 8Ts HNDP = Horizontal Non-Display Period = HT - HDP = (((REG[20h] bits 6: 8Ts) - (((REG[24h] bits 6: 8Ts) S1D13A05 X40A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP Ts ...
Page 73
... Revision 6. t11 t10 t12 t13 1 2 Min Typ Max Units note 2 Ts (note 1) note 3 note 4 note 5 note 6 note t14 + note 8 S1D13A05 X40A-A-001-06 Page ...
Page 74
... Vertical Non-Display Period = VT - VDP = (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines HDP = Horizontal Display Period = ((REG[24h] bits 6: 8Ts HNDP = Horizontal Non-Display Period = HT - HDP = (((REG[20h] bits 6: 8Ts) - (((REG[24h] bits 6: 8Ts) S1D13A05 X40A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 HDP 2Ts 3Ts ...
Page 75
... Parameter min ), if negative add t3 min Revision 6. t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 note 4 note 5 note 6 note t14 + note 8 X40A-A-001-06 Page 69 Units S1D13A05 ...
Page 76
... TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8. *Panel Type Bits (REG[0Ch] bits 1- (TFT) *FPLINE Pulse Polarity Bit (REG[2Ch] bit 23 (active low) *FPFRAME Polarity Bit (REG[3Ch] bit 23 (active low) S1D13A05 X40A-A-001- Frame) VPW ...
Page 77
... Horizontal Non-Display Period 2 = HPS - (HDP + HDPS) Ts Hardware Functional Specification Issue Date: 2005/05/19 VNDP 2 LINE1 HDP HNDP 1 invalid 1-1 1-2 Figure 6-28: 18-Bit TFT Panel Timing if negative add VT if negative add HT if negative add HT Revision 6.01 Page 71 VDP VNDP 1 LINE480 HNDP 2 1-320 invalid S1D13A05 X40A-A-001-06 ...
Page 78
... Page 72 FPFRAME t3 FPLINE FPLINE DRDY t9 t10 t11 FPSHIFT FPDAT[17:0] Note: DRDY is used to indicate the first pixel S1D13A05 X40A-A-001- t12 invalid Figure 6-29: TFT A.C. Timing Revision 6.01 Epson Research and Development Vancouver Design Center t13 t14 t15 t16 1 2 319 320 ...
Page 79
... HPS - (HDP + HDPS) Hardware Functional Specification Issue Date: 2005/05/19 Table 6-26: TFT A.C. Timing Parameter if negative add HT if negative add HT Revision 6.01 Page 73 Min Typ Max Units VT Lines VPW Lines HPS Ts (note HPW Ts note 2 250 Ts HDP Ts note 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts S1D13A05 X40A-A-001-06 ...
Page 80
... GPIO0 (PS2) first falling edge to GPIO0 (PS2) first rising edge t11 GPIO0 (PS3) pulse width t12 GPIO2 (REV) toggle position to FPLINE (LP) rising edge pixel clock period 2. t1typ = [(REG[20h] bits 6- t2typ = [((REG[24h] bits 6- t3typ = [(REG[24h] bits 6- S1D13A05 X40A-A-001- t10 ...
Page 81
... Parameter Revision 6.01 Vertical Display Period t7 Driving period for PS3 Min Typ Max Units Lines 1 note 3 8 (note 1) 1 note 4 1024 Lines 1 Ts (note 2) (note 5) 0 note 5 1023 0 note 6 1023 Lines 1 note 7 1024 Lines 0 note 8 7 Lines S1D13A05 X40A-A-001-06 Page 75 Ts ...
Page 82
... S1D13A05 X40A-A-001- t10 t9 t11 Figure 6-32: Casio TFT Horizontal Timing Table 6-29: Casio TFT Horizontal Timing Parameter Revision 6 ...
Page 83
... Issue Date: 2005/05/ Figure 6-33: Casio TFT Vertical Timing Table 6-30: Casio TFT Vertical Timing Parameter Revision 6. Min Typ Max Units 1 note 2 1024 lines (note 1) 0 note 3 1023 lines 1 note 4 8 lines 1 note 5 1024 lines 1 note 6 1024 lines S1D13A05 X40A-A-001-06 Page 77 ...
Page 84
... Data setup time t8 Data hold time Horizontal display period t9 t10 FPLINE (STB) rising edge to GPIO1 (AP) rising edge t11 GPIO1 (AP) pulse width t12 FPLINE (STB) rising edge to GPIO2 (POL) toggle position S1D13A05 X40A-A-001- t10 t12 Figure 6-34: TFT Type 2 Horizontal Timing ...
Page 85
... Hardware Functional Specification Issue Date: 2005/05/19 t1 Line1 Line2 Figure 6-35: TFT Type 2 Vertical Timing Table 6-32: TFT Type 2 Vertical Timing Parameter Revision 6.01 Page 79 t5 Last Min Typ Max Units 8 1024 Lines 1 Lines 0 Ts (note 1) 0 note 3 1024 Lines (note 2) 1 note 4 1024 Ts S1D13A05 X40A-A-001-06 ...
Page 86
... TFT Type 3 Panel Timing t2 FPLINE (LP) GPIO3 (EIO) FPSHIFT (CPH) D[17:0] DRDY (INV) GPIO1 (OE) GPIO2 (POL) GPO1 (VCOM) t13 GPIO0 (CPV) S1D13A05 X40A-A-001- t11 t12 t14 Figure 6-36: TFT Type 3 Horizontal Timing Revision 6.01 Epson Research and Development Vancouver Design Center t8 2 t10 ...
Page 87
... Hardware Functional Specification Issue Date: 2005/05/19 Table 6-33: TFT Type 3 Horizontal Timing Parameter Revision 6.01 Page 81 Min Typ Max Units 8 1024 Ts (note 1) 1 256 0 1024 Ts 0 512 Ts 0 512 Ts 0 512 Ts 0 512 512 Ts S1D13A05 X40A-A-001-06 ...
Page 88
... GPO2 (XOEV) GPIO2 (POL) (Odd Frame) GPO1 (VCOM) (Odd Frame) GPIO2 (POL) (Even Frame) GPO1 (VCOM) (Even Frame) S1D13A05 X40A-A-001- Line1 Line2 Figure 6-37: TFT Type 3 Vertical Timing Revision 6.01 Epson Research and Development Vancouver Design Center Last Hardware Functional Specification ...
Page 89
... Hardware Functional Specification Issue Date: 2005/05/19 Table 6-34: TFT Type 3 Vertical Timing Parameter Revision 6.01 Page 83 Min Typ Max Units 1 1024 Lines 1 Lines 0.5 Lines 1 Lines 1 1024 Lines 0 512 Ts 0 512 Ts S1D13A05 X40A-A-001-06 ...
Page 90
... Page 84 6.4.14 TFT Type 4 Panel Timing FPFRAME FPLINE FPDAT[17:0] LINE480 DRDY FPLINE FPSHIFT DRDY FPDAT[17:0] Note: DRDY is used to indicate the first pixel Example Timing for 12-bit 640x480 panel S1D13A05 X40A-A-001-06 VNDP 2 LINE1 HDP HNDP 1 invalid 1-1 1-2 Figure 6-38: TFT Type 4 Panel Timing Revision 6.01 ...
Page 91
... HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2 = HT - HDP Ts HNDP1 = Horizontal Non-Display Period 1 = HDPS - (HPS + HNDP2 = Horizontal Non-Display Period 2 = (HPS + 1) - (HDP + HDPS + 5) Ts Hardware Functional Specification Issue Date: 2005/05/19 if negative add VT if negative add HT if negative add HT Revision 6.01 Page 85 S1D13A05 X40A-A-001-06 ...
Page 92
... Page 86 FPFRAME t3 FPLINE FPLINE DRDY t10 t11 t12 FPSHIFT FPDAT[17:0] Note: DRDY is used to indicate the first pixel S1D13A05 X40A-A-001- t13 t14 invalid Figure 6-39: TFT Type 4 A.C. Timing Revision 6.01 Epson Research and Development Vancouver Design Center t15 t16 t17 ...
Page 93
... Hardware Functional Specification Issue Date: 2005/05/19 Table 6-35: TFT Type 4 A.C. Timing Parameter if negative add HT if negative add HT Revision 6.01 Page 87 Min Typ Max Units VT Lines VPW Lines HPS + 1 Ts (note HPW Ts note 2 250 HDP Ts note 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts 0.5 Ts S1D13A05 X40A-A-001-06 ...
Page 94
... Page 88 6.5 USB Timing Data Signal Rise and Fall Time Figure 6-42 Differential to EOP Transition Skew and EOP Width S1D13A05 X40A-A-001-06 Figure 6-40 Data Signal Rise and Fall Time Figure 6-41 Differential Data Jitter Revision 6.01 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
Page 95
... Note 4 Figure 6-43 Note 4 Figure 6-43 Note 4 Figure 6-42 Note 4 Figure 6-42 Revision 6.01 Page 89 Min Typ Max Unit 48 MHz 1 ------------------------ - USB FREQ 110 % 1.3 2.0 Note 11.97 12 12.03 Mbs -3.5 0 3.5 ns -4 160 167 175 ns -18 S1D13A05 X40A-A-001-06 V Ω ...
Page 96
... MCLK MCLK provides the internal clock required to access the embedded SRAM. The S1D13A05 is designed with efficient power saving control for clocks (clocks are turned off when not used); reducing the frequency of MCLK does not necessarily save more power. Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and so reduces screen update performance ...
Page 97
... REG[08h] bits 7-0 = 22h ÷ CLKI 4 REG[08h] bits 7-0 = 32h ÷ CLKI 8 REG[08h] bits 7-0 = 42h CLKI2 REG[08h] bits 7-0 = 03h ÷ CLKI2 2 REG[08h] bits 7-0 = 13h ÷ CLKI2 3 REG[08h] bits 7-0 = 23h ÷ CLKI2 4 RREG[08h] bits 7-0 = 33h ÷ CLKI2 8 REG[08h] bits 7-0 = 43h Revision 6.01 Page 91 S1D13A05 X40A-A-001-06 ...
Page 98
... PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel. The source clock options for PWMCLK may be selected as in the following table. For further information on controlling PWMCLK, see “PWM Clock Configuration Register” on page 126.. S1D13A05 X40A-A-001-06 Table 7-4: Relationship between MCLK and PCLK Color Depth (bpp) ...
Page 99
... Epson Research and Development Vancouver Design Center 7.2 Clock Selection The following diagram provides a logical representation of the S1D13A05 internal clocks used for the LCD controller. CLKI CLKI2 Note 1 CNF6 must be set at RESET#. Hardware Functional Specification Issue Date: 2005/05/ ÷ CNF6 ...
Page 100
... Page 94 7.3 Clocks versus Functions Table 7-6: “S1D13A05 Internal Clock Requirements”, lists the internal clocks required for the following S1D13A05 functions. Table 7-6: S1D13A05 Internal Clock Requirements Bus Clock Function (BCLK) Register Read/Write Required Memory Read/Write Required Look-Up Table Register Required Read/Write Software Power Save ...
Page 101
... Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13A05 registers. It also provides detailed information about the layout and usage of each register. 8.1 Register Mapping The S1D13A05 registers are memory-mapped. When the system decodes the input pins as CS and M/ the registers may be accessed ...
Page 102
... Page 96 8.2 Register Set The S1D13A05 register set is as follows. Register REG[00h] Product Information Register REG[04h] Memory Clock Configuration Register REG[0Ch] Panel Type & MOD Rate Register REG[14h] Power Save Configuration Register REG[18h] Look-Up Table Write Register REG[20h] Horizontal Total Register REG[28h] Horizontal Display Period Start Position Register ...
Page 103
... REG[8020h] BitBLT Background Color Register 2D Acceleration (BitBLT) Data Register Descriptions (Offset = 10000h) AB16-AB0 = 10000h-1FFFEh, 2D Accelerator (BitBLT) Data Memory Mapped Region Register Hardware Functional Specification Issue Date: 2005/05/19 Table 8-2: S1D13A05 Register Set Pg 143 REG[4010h] Endpoint 1 Index Register 144 REG[4018h] Endpoint 2 Index Register ...
Page 104
... Display Buffer Size Bits [7:0] This is a read-only register that indicates the size of the SRAM display buffer measured in 4K byte increments. The S1D13A05 display buffer is 256K bytes and therefore this regis- ter returns a value of 64 (40h). Value of this register = display buffer size ÷ 4K bytes ...
Page 105
... Changing this bit allows the BCLK source to be switched in a glitch-free manner. Hardware Functional Specification Issue Date: 2005/05/ Table 8-3: MCLK Divide Selection Revision 6.01 Read/Write MCLK Divide n/a Select bits 1 BCLK to MCLK Frequency Ratio 1:1 2:1 3:1 4:1 X40A-A-001-06 Page 99 16 BCLK Source Select 0 S1D13A05 ...
Page 106
... These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel Clock Source. PCLK Divide Select Bits bits 1-0 PCLK Source Select Bits [1:0] These bits determine the source of the Pixel Clock (PCLK). PCLK Source Select Bits S1D13A05 X40A-A-001-06 n ...
Page 107
... Table 8-6: Panel Data Width Selection Passive Panel Data Width Size 4-bit 8-bit 16-bit Reserved Revision 6.01 Read/Write MOD Rate bits 5 Panel Data Width Reserv Panel Type n/a bits 1-0 ed bits 1 Active Panel Data Width Size 9-bit 12-bit 18-bit Reserved S1D13A05 X40A-A-001-06 Page 101 16 0 ...
Page 108
... When this bit = 1, pixel doubling in the horizontal dimension (width) is enabled. When this bit = 0, there is no hardware effect. Note Pixel Doubling is not supported in SwivelView 90° or SwivelView 270° modes. S1D13A05 X40A-A-001-06 Table 8-7: LCD Panel Type Selection Panel Type 00 ...
Page 109
... Software Video Invert (REG[10h] bit 21) (REG[10h] bit 20 gray shades in 1/2/4/8 bpp mode. In 16bpp mode, only 64K colors gray shades. Revision 6.01 Page 103 Output Data Lines (FPDAT[17:0]) Normal Inverted All 0 All 1 All 1 All 0 S1D13A05 X40A-A-001-06 ...
Page 110
... LUT. 16 bpp mode bypasses the LUT. For further details on the LUT, refer to Section 12, “Look-Up Table Architecture” on page 168. Bit-per-pixel Select Bits [4:0] 00000 00001 00010 00011 00100 00101 - 00111 01000 10000 10001 - 11111 S1D13A05 X40A-A-001-06 orientations Table 8-9: SwivelView Mode Select Options SwivelView Orientation window (if active) ...
Page 111
... When this bit = 1, the memory controller is powered down and the MCLK source can be turned off. Note Memory reads/writes are possible during power save mode because the S1D13A05 dy- namically enables the memory controller for display buffer accesses. bit 4 Power Save Mode Enable When this bit = 1, the software initiated power save mode is enabled ...
Page 112
... These bits contains the data to be written to the blue component of the Look-Up Table. The LUT position is controlled by the LUT Write Address bits (bits 31-24). When the S1D13A05 is set to a host bus interface using big endian (CNF4 = 1), the RGB data is updated to the LUT with the completion of a write to these bits. ...
Page 113
... Note The S1D13A05 has three 256-position, 6-bit wide LUTs, one for each of red, green, and blue (see Section 12, “Look-Up Table Architecture” on page 168). bits 31-24 LUT Read Address Bits [7:0] (Write Only) This register forms a pointer into the Look-Up Table (LUT) which is used to read LUT data ...
Page 114
... For passive panels, HDP must be a minimum of 32 pixels and must be increased by mul- tiples of 16. For TFT panels, HDP must be a minimum of 8 pixels and must be increased by multi- ples of 8. Note See Section 6.4, “Display Interface” on page 56. S1D13A05 X40A-A-001-06 n ...
Page 115
... Horizontal Display Period Start Position bits 9 FPLINE Polarity FPLINE Pulse Start Position bits 9 Revision 6.01 Page 109 Read/Write Read/Write FPLINE Pulse Width bits 6 S1D13A05 X40A-A-001- ...
Page 116
... Vertical Total is 1024 lines. REG[30h] bits 9:0 = Vertical Total in number of lines - 1 Note 1 This register must be programmed such that the following formula is valid HR-TFT panel is selected, the following formula must also apply. 3 See Section 6.4, “Display Interface” on page 56. S1D13A05 X40A-A-001-06 n ...
Page 117
... VT > (REG[B8h] bits 2-0) + VDP + VPS + 1 n Vertical Display Period Start Position bits 9 > VDPS + VDP VT > (REG[B8h] bits 2-0) + VDP + VPS + 1 Revision 6.01 Page 111 Read/Write Read/Write S1D13A05 X40A-A-001- ...
Page 118
... These bits specify the start position of the vertical sync signal line resolution. For passive panels, these bits must be set to 00h. For TFT panels, VDPS is calculated using the following formula. VPS = REG[3Ch] bits 9-0 Note See Section 6.4, “Display Interface” on page 56. S1D13A05 X40A-A-001-06 FPFRAME Polarity 26 25 ...
Page 119
... Main Window Display Start Address bits 15 n Main Window Line Address Offset bits 9 Revision 6.01 Page 113 Read/Write Read/Write S1D13A05 X40A-A-001-06 bit ...
Page 120
... When this bit = 1, the Data Compare and Invert functions are enabled. bits 3-0 Extended Panel Type Bits [3:0] These bits override the setting in REG[0Ch] bits 1-0 and allow selection of the alternate TFT panel types. REG[48h] Bits [3:0] 0000 0001 0010 0011 0100 0101 - 1111 S1D13A05 X40A-A-001-06 n Data Compare Invert Enable ...
Page 121
... PIP Line Address Offset bits 9 Window Enable bit is set to 1 (REG[10h] bit Revision 6.01 Page 115 Read/Write Read/Write window. Note that this is a S1D13A05 X40A-A-001-06 bit ...
Page 122
... Window X End Position Bits [9:0] These bits determine the X end position of the PIP panel. Due to the S1D13A05 SwivelView feature, the X end position may not be a horizontal position value (only true in 0° and 180° SwivelView). For further information on defining the value of the X End Position register, see Section 14, “ ...
Page 123
... Window X Start Position Bits [9:0] These bits determine the X start position of the PIP panel. Due to the S1D13A05 SwivelView feature, the X start position may not be a horizontal position value (only true in 0° and 180° SwivelView). For further information on defining the value of the X Start Position register, see Section 14, “ ...
Page 124
... Window Y End Position Bits [9:0] These bits determine the Y end position of the PIP panel. Due to the S1D13A05 SwivelView feature, the Y end position may not be a vertical position value (only true in 0° and 180° SwivelView). For further information on defining the value of the Y End Position register, see Section 14, “ ...
Page 125
... Window Y Start Position Bits [9:0] These bits determine the Y start position of the PIP panel. Due to the S1D13A05 SwivelView feature, the Y start position may not be a vertical position value (only true in 0° and 180° SwivelView). For further information on defining the value of the Y Start Position register, see Section 14, “ ...
Page 126
... The S1D13A05 GPIO pins default to inputs, however they can be individually configured to outputs or inputs using the GPIO[7:0] Config bits (bits 23-16 GPIO pin is configured as an input, the input functionality must be enabled using the corresponding GPIO[7:0] Input Enable pin (see bits 31-24). Once the GPIO pin has been configured, it can be controlled/read using the GPIO[7:0] Control/Status bits (bits 7-0) ...
Page 127
... GPIO6 driven high Table 8-18: GPIO5 Usage Function Output Write 0 Write 1 GPIO5 driven high not available (used by USBDETECT) Revision 6.01 Page 121 Input Read GPIO7 status returned Input Read GPIO6 status returned Input Read GPIO5 status returned not available (used by USBDETECT) S1D13A05 X40A-A-001-06 ...
Page 128
... GPIO2 driven low Sharp HR-TFT not available (used by REV) Casio TFT not available (used by FRP) TFT Type 2 not available (used by POL) TFT Type 3 not available (used by POL) S1D13A05 X40A-A-001-06 Table 8-19: GPIO4 Usage Function Output Write 0 Write 1 GPIO4 driven high not available (used by ...
Page 129
... GPIO0 status returned not available (used by PS) not available (used by POL) not available (used by VCLK) not available (used by CPV) Read/Write GPO5 GPO4 GPO3 GPO2 GPO1 Control Control Control Control Control S1D13A05 X40A-A-001-06 Page 123 16 GPO0 Control 0 ...
Page 130
... GPO3 high and writing this bit drives GPO3 low. A read from this bit returns the status of GPO3. When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), GPO3 is not available. S1D13A05 X40A-A-001-06 Epson Research and Development Hardware Functional Specification Revision 6 ...
Page 131
... VCOM and writing a 0 sets VCOM = 0. bit 0 GPO0 Control Writing this bit drives GPO0 high and writing this bit drives GPO0 low. A read from this bit returns the status of GPO0. Hardware Functional Specification Issue Date: 2005/05/19 Revision 6.01 Page 125 S1D13A05 X40A-A-001-06 ...
Page 132
... Table 8-24: PWM Clock Divide Select Options PWM Clock Divide Select Bits [3: S1D13A05 X40A-A-001-06 n PWM Clock Divide Select bits 3 PWM Clock Enable Divided PWM Duty Cycle Clock Modulation ...
Page 133
... High for 1 out of 256 clock periods High for 2 out of 256 clock periods High for 255 out of 256 clock periods Revision 6.01 Page 127 PWMCLK Source CLKI CLKI2 BCLK PCLK Read/Write PWMOUT Duty Cycle bits 7 Always Low ... S1D13A05 X40A-A-001- ...
Page 134
... This register contains general purpose read/write bits. These bits have no effect on hard- ware. Note The contents of the Scratch Pad A register defaults to an un-defined state after initial power-up. Any data written to this register remains intact when the S1D13A05 is reset, as long as the chip is not powered off. Scratch Pad B Register REG[84h] ...
Page 135
... Revision 6.01 Page 129 Read/Write CLS Pulse Width bits 8 Read/Write PS1 Rising Edge bits 5 Read/Write PS2 Rising Edge bits 7 S1D13A05 X40A-A-001- ...
Page 136
... HR-TFT REV Toggle Point Register REG[B4h] Default = 0000000Ah bits 4-0 REV Toggle Bits [4:0] This register determines the width in PCLKs to toggle the REV signal prior to LP rising edge. S1D13A05 X40A-A-001-06 n (REG[ACh] bits 6-0) > ...
Page 137
... When this bit = 1, the POL signal is toggled every frame. bits 13-11 AP Pulse Width Bits [2:0] These bits specify the AP Pulse Width used for the TFT Type 2 Interface. The S1D13A05 GPIO1 pin controls the AP signal for the TFT Type 2 Interface. For all other panel inter- faces it has no effect. ...
Page 138
... These bits specify the TFT Type 2 AC timing parameter from the rising edge of GPIO0 (VCLK) to the rising edge of FPLINE (STB). The parameter is selected as follows. For all other panel interfaces it has no effect. REG[4Ch] bits 1-0 S1D13A05 X40A-A-001-06 Table 8-28: AP Rising Position AP Rising Position (in PCLKs) ...
Page 139
... OE Rising Edge Position Bits [7:0] These bits specify the rising edge position of the OE signal in 2 pixel resolution. The S1D13A05 GPIO1 pin controls the OE signal used for the TFT Type 3 Interface. This reg- ister has no effect for all other panel interfaces. OE Rising Edge Position in pixels = (REG[D8h] bits 15-8) × 2 ...
Page 140
... If this register is set pulse is generated. bits 15-8 CPV Pulse Width Bits [7:0] These bits specify the pulse width of the CPV signal in 2 pixel resolution. The S1D13A05 GPIO0 pin controls the CPV signal used for the TFT Type 3 Interface. This register has no effect for all other panel interfaces. ...
Page 141
... Revision 6.01 Page 135 Read/Write PCLK2 Divide PCLK1 Divide Rate bits 3-0 Rate bits 1 S1D13A05 X40A-A-001- ...
Page 142
... Area 0 Display Enable This bit enables/disables the Area 0 for Partial Mode Display on the TFT Type 3 and has no effect for all other panel interfaces. When this bit = 1, Area 0 is enabled. When this bit = 0, Area 0 is disabled. S1D13A05 X40A-A-001-06 n ...
Page 143
... Revision 6.01 Page 137 Read/Write Partial Area 0 X End Position bits 5 Partial Area 0 X Start Position bits 5 Read/Write Partial Area 1 X End Position bits 5 Partial Area 1 X Start Position bits 5 S1D13A05 X40A-A-001- ...
Page 144
... These bits store command 1 for the TFT Type 3 Interface. This register has no effect for all other panel interfaces. bits 11-0 Command 0 Store Bits [11:0] These bits store command 0 for the TFT Type 3 Interface. This register has no effect for all other panel interfaces. S1D13A05 X40A-A-001-06 n ...
Page 145
... Table 8-33: Number of Source Driver ICs REG[E0h] bits 1-0 bit 0 Command Send Request After the CPU sets this bit, the S1D13A05 sends the command in the next non-display period and clears this bit automatically. This register has no effect for all other panel inter- faces. Hardware Functional Specification ...
Page 146
... If this bit is asserted, the S1D13A05 responds request to Endpoint 4 with an ACK and a zero length packet if the FIFO is empty. If this bit is not asserted, the S1D13A05 responds request from Endpoint 4 with an NAK if the FIFO is empty, indicating that it expects to transmit more data. This bit is automatically cleared when the S1D13A05 responds to the host with a zero length packet when the FIFO is empty ...
Page 147
... Endpoint 4 Stall. If this bit is set, host bulk reads from the transmit FIFO will result in a STALL acknowl- edge by the S1D13A05. No data will be returned to the USB host. bit 3 Endpoint 3 Stall. If this bit is set, host bulk writes to the receive FIFO will result in a STALL acknowledge by the S1D13A05 ...
Page 148
... Writing a 1 clears this bit. bit 3 Endpoint 3 Interrupt Status (Receive FIFO Valid). This bit indicates when a USB Endpoint 3 Data packet has been received by the S1D13A05. No more packets to endpoint 3 will be accepted until this bit is cleared. Writ- ing a 1 clears this bit. bit 2 Endpoint 2 Interrupt Status. ...
Page 149
... Issue Date: 2005/05/ Revision 6.01 Page 143 Read/Write Transmit FIFO Receive FIFO Almost Empty Almost Full Interrupt Enable Interrupt Enable Read/Write Transmit FIFO Receive FIFO Almost Empty Almost Full Status Status S1D13A05 X40A-A-001-06 ...
Page 150
... This register determines which Endpoint 2 Transmit Mailbox is accessed when the End- point 2 Transmit Mailbox Data register is read or written. This register is automatically incremented after the Endpoint 2 Transmit Mailbox Data port is read or written. This index register wraps around to zero when it reaches the maximum count (7). S1D13A05 X40A-A-001-06 n/a 13 ...
Page 151
... Interrupt Polling Interval bits 7 n Endpoint 3 Receive FIFO Data bits 7 n Receive FIFO Count bits 7 Revision 6.01 Page 145 Read/Write Read/Write Read Only Read Only S1D13A05 X40A-A-001-06 ...
Page 152
... Default = 00h bits 7-0 Transmit FIFO Data Bits [7:0]. This register is used by the local CPU to write data to the transmit FIFO. The FIFO data is read by the USB host using bulk or isochronous transfers from endpoint 4. S1D13A05 X40A-A-001-06 n Receive FIFO Receive FIFO Flush ...
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... Transmit FIFO Flush Overflow n Endpoint 4 Max Packet Size bits 7 Revision 6.01 Page 147 Read Only Read/Write Transmit FIFO Transmit FIFO Reserved Full (read only) Empty (read only Read/Write S1D13A05 X40A-A-001-06 ...
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... Suspend Control If set, this bit indicates that there is a pending suspend request. Writing a 1 clears this bit and causes the S1D13A05 USB device to enter suspended mode. bit 6 USB Endpoint 4 STALL The last USB IN token could not be serviced because the endpoint was stalled (REG[4000h] bit 4 set), and was acknowledged with a STALL ...
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... Default = 04h Vendor ID bits 15 Default = B8h Vendor ID bits 7 Revision 6.01 Page 149 Read Only Frame Counter bits 10 Read Only Read/Write Read/Write Read/Write Read/Write S1D13A05 X40A-A-001-06 ...
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... This register determines the threshold at which the receive FIFO almost full status bit is set. Note The Receive FIFO Almost Full threshold must be set less than 64, as the FIFO count must rise above the threshold to cause an interrupt. S1D13A05 X40A-A-001-06 Default = 88h Product ID bits 15-8 5 ...
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... Maximum Current Bits [7:0]. The amount of current drawn by the peripheral from the USB port in increments of 2 mA. The S1D13A05 reports this value to the host controller in the configuration descriptor. The default and maximum value is 500 mA (FAh * 2 mA). In order to comply with the USB specification the following formula must apply: ...
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... When a write is made to this bit, the value cannot be read back before a minimum of 12 USBCLK. bit 3 Reserved. This bit must be set to 0. bit 2 Reserved. This bit must be set to 0. bit 0 Reserved. This bit must be set to 0. S1D13A05 X40A-A-001-06 Default = 00h EP1 Data Toggle Reserved Revision 6.01 Epson Research and Development Vancouver Design Center ...
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... This bit must be set to 0. Hardware Functional Specification Issue Date: 2005/05/19 Default = 00h n Default = 00h n n Reserved ISO Revision 6.01 Page 153 Read/Write Reserved Read/Write Transmit FIFO Valid Mode Read/Write WAKEUP Reserved Reserved S1D13A05 X40A-A-001-06 ...
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... USBPUP Output Pin Status This bit controls the state of the USBPUP output pin. This bit must be set enable the USB interface and USB registers. See the S1D13A05 Programming Notes and Examples, document number X40-A-G-003-xx for further infor- mation on this bit. ...
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... Indicates the USB device is reset using the RESET# pin or using the USB port reset. bit 0 Reserved. Must be set to 0. Hardware Functional Specification Issue Date: 2005/05/19 n Device Reserved Configured n Reserved Reserved Revision 6.01 Page 155 Read/Write Reserved Reserved INT Read/Write Reserved USBRESET Reserved S1D13A05 X40A-A-001-06 ...
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... Reserved. Must be set to 0. bit 2 Reserved. Must be set to 0. bit 1 Reserved. Must be set to 0. bit 0 INT Indicates an interrupt request originating from within the USB registers (REG[4000h] to REG[403Ah]). S1D13A05 X40A-A-001-06 n Device Reserved Configured Revision 6.01 Epson Research and Development ...
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... USB Wait State Bits [1:0] This register controls the number of wait states the S1D13A05 uses for its internal USB support. For all bus interfaces supported by the S1D13A05 these bits must be set to 01. Hardware Functional Specification Issue Date: 2005/05/19 n ...
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... Page 158 8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h) These registers control the S1D13A05 2D Acceleration engine. For detailed BitBLT programming instructions, see the S1D13A05 Programming Notes and Examples, document number X40A-G-003-xx. BitBLT Control Register REG[8000h] Default = 00000000h ...
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... Revision 6.01 Read Only Number of Free FIFO Entries (0 means full FIFO FIFO Full n/a Half Full Status Number of Words available in BitBLT FIFO S1D13A05 X40A-A-001-06 Page 159 16 BitBLT Busy Status 0 ...
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... 1001 ~( 1010 D 1011 ~ 1100 S 1101 1110 1111 1 (Whiteness) Note S = Source Destination Pattern NOT Logical AND Logical OR Logical XOR S1D13A05 X40A-A-001- Boolean Function for Pattern Fill 0 (Blackness ~( ...
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... Transparent Write BitBLT. Transparent Move BitBLT in positive direction. Pattern Fill with ROP. Pattern Fill with transparency. Color Expansion. Color Expansion with transparency. Move BitBLT with Color Expansion. Move BitBLT with Color Expansion and transparency. Solid Fill. Reserved Revision 6.01 Page 161 S1D13A05 X40A-A-001-06 ...
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... Pattern Base Address[20:0] 8 bpp BitBLT Source Start Address[20:6] 16 bpp BitBLT Source Start Address[20:7] Note For further information on the BitBLT Source Start Address register, see the S1D13A05 Programming Notes and Examples, document number X40A-G-003-xx. BitBLT Destination Start Address Register REG[8010h] Default = 00000000h 31 ...
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... BitBLT Width bits 9 n BitBLT Height bits 9 Revision 6.01 Page 163 Read/Write Read/Write Read/Write S1D13A05 X40A-A-001- ...
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... Accelerator (BitBLT) Data Memory Mapped Region Register AB16-AB0 = 10000h-1FFFEh, even addresses bits 15-0 BitBLT Data Bits [15:0] This register specifies the BitBLT data. This register is loosely decoded from 10000h to 1FFFEh. S1D13A05 X40A-A-001-06 n BitBLT Background Color bits 15 n/a 26 ...
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... Vancouver Design Center 9 2D Accelerator (BitBLT) Engine 9.1 Overview The S1D13A05 is designed with a built-in 2D BitBLT engine which increases the perfor- mance of Bit Block Transfers (BitBLT). It supports 8 and 16 bit-per-pixel color depths. The BitBLT engine supports rectangular and linear addressing modes for source and desti- nation in a positive direction for all BitBLT operations except the move BitBLT which also supports in a negative direction ...
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... Page 166 10 Frame Rate Calculation The following formula is used to calculate the display frame rate. Where: f PCLK HT VT S1D13A05 X40A-A-001-06 f PCLK FrameRate = ------------------------------- - ( HT ) × PClk frequency (Hz) = Horizontal Total = ((REG[20h] bits 6- Pixels = Vertical Total = ((REG[30h] bits 9- Lines Revision 6.01 Epson Research and Development ...
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... Panel Display RGB value from LUT Index Panel Display 4-0 5-0 4 Panel Display S1D13A05 X40A-A-001-06 ...
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... Green Look-Up Table 256x6 bit-per-pixel data from Display Buffer Figure 12-2: 2 Bit-per-pixel Monochrome Mode Data Output Path S1D13A05 X40A-A-001-06 Epson Research and Development 6-bit Gray Data unused Look-Up Table entries 00 6-bit Gray Data unused Look-Up Table entries Hardware Functional Specification Revision 6 ...
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... Gray Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Revision 6.01 Page 169 S1D13A05 X40A-A-001-06 ...
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... FE FF Blue Look-Up Table 256x6 bit-per-pixel data from Image Buffer Figure 12-5: 1 Bit-Per-Pixel Color Mode Data Output Path S1D13A05 X40A-A-001-06 Epson Research and Development 6-bit Red Data 0 1 6-bit Green Data 0 1 6-bit Blue Data unused Look-Up Table entries Hardware Functional Specification Revision 6 ...
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... Image Buffer Figure 12-6: 2 Bit-Per-Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date: 2005/05/19 00 6-bit Red Data 6-bit Green Data 6-bit Blue Data unused Look-Up Table entries Revision 6.01 Page 171 S1D13A05 X40A-A-001-06 ...
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... bit-per-pixel data from Image Buffer Figure 12-7: 4 Bit-Per-Pixel Color Mode Data Output Path S1D13A05 X40A-A-001-06 Epson Research and Development 0000 0001 0010 0011 0100 0101 0110 6-bit Red Data 0111 1000 1001 1010 1011 ...
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... Blue Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Revision 6.01 Page 173 S1D13A05 X40A-A-001-06 ...
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... Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK. The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13A05 in the following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following sense: B-D-A-C ...
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... REG[44h] bits 9:0 Hardware Functional Specification Issue Date: 2005/05/19 = ((image address + (panel height x bpp ÷ 8)) ÷ ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ (4Fh) = display width in pixels ÷ (32 ÷ bpp) = 320 pixels ÷ 32 ÷ 8 bpp = 80 (50h) Revision 6.01 Page 175 S1D13A05 X40A-A-001-06 ...
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... SwivelView™ The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13A05 in the following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following sense: D-C-B-A. ...
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... Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK. The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13A05 in the following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following sense: C-A-D-B ...
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... The Main Window Line Address Offset register (REG[44h]) is based on the display width and programmed using the following formula. REG[44h] bits 9:0 S1D13A05 X40A-A-001-06 = (image address + ((panel width - 1) x offset x bpp ÷ 8) ÷ ((480 pixels - 1) x 320 pixels x 8 bpp ÷ 8) ÷ 38320 (95B0h) = display width in pixels ÷ ...
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... SwivelView orientation PIP window y start position (REG[5Ch] bits 9-0) + PIP window y end position (REG[5Ch] bits 25-16) main-window + PIP window + PIP window x end position (REG[58h] bits 25-16) Revision 6.01 Page 179 + window) within the window within a main window and the S1D13A05 X40A-A-001-06 ...
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... Figure 14-2: Picture-in-Picture Plus with SwivelView 90° enabled 14.2.2 SwivelView 180° TM 180° SwivelView PIP + PIP window y end position (REG[5Ch] bits 25-16) Figure 14-3: Picture-in-Picture Plus with SwivelView 180° enabled S1D13A05 X40A-A-001-06 panel’s origin PIP (REG[58h] bits 9-0) + PIP window PIP (REG[5Ch] bits 9-0) ...
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... PIP window x start position (REG[58h] bits 9-0) panel’s origin Figure 14-4: Picture-in-Picture Plus with SwivelView 270° enabled Hardware Functional Specification Issue Date: 2005/05/19 main-window + PIP window + PIP window x end position (REG[58h] bits 25-16) Revision 6.01 Page 181 S1D13A05 X40A-A-001-06 ...
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... The power-down state of the USB section is controlled by the USBClk Enable bit (REG[4000h] bit 7). After reset, the S1D13A05 is always in Power Save Mode. Software must initialize the chip (i.e. programs all registers) and then clear the Power Save Mode Enable bit. S1D13A05 X40A-A-001-06 ...
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... Table 16-1: Resistance and Capacitance Values for Example Circuit Hardware Functional Specification Issue Date: 2005/05/19 USBOSCI USBOSCO Figure 16-1: USB Oscillator Example Circuit Symbol Revision 6. Value 1MΩ 470Ω 12pF 12pF X40A-A-001-06 Page 183 S1D13A05 ...
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... Page 184 17 Mechanical Data TOP VIEW All dimensions in mm Figure 17-1: Mechanical Data PFBGA 121-pin Package S1D13A05 X40A-A-001-06 +0.30 10 -0.15 +0.10 0.45 -0.05 0. BOTTOM VIEW Revision 6.01 Epson Research and Development Vancouver Design Center 1.2max +0.10 0.35 -0.05 0.1max SIDE VIEW 1 ...
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... Vancouver Design Center 102 103 128 1 15° ±0.1 3.5 max 2.7 0.35 15° All dimensions in mm Figure 17-2: Mechanical Data QFP5 128-pin Package Hardware Functional Specification Issue Date: 2005/05/19 ±0.4 23.2 ±0 INDEX ±0.05 38 0.22 0.5 0.8 1.6 Revision 6.01 Page 185 64 ±0.1 ±0.4 14 17.2 39 0.2 0.2 ±0.05 0.15 0-10° ±0.2 0.8 S1D13A05 X40A-A-001-06 ...
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... Page 186 18 References The following documents contain additional information related to the S1D13A05. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • S1D13A05 Product Brief (X40A-C-001-xx) • S1D13A05 Programming Notes And Examples (X40A-G-003-xx) • ...
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... Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/ S1D13A05 X40A-A-001-06 ...
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... QFP package mechanical drawing X40A-A-001-05 Revision 5.0 • released as revision 5.0 X40A-A-001-04 Revision 4.01 • section 4.2.2, for DRDY pin description, removed description for HR-TFT (not used) S1D13A05 X40A-A-001-06 Change Record Revision 6.01 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
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... Errata No. X00Z-P-001-01 Device: S1D13A03, S1D13A04, S1D13A05. Description: Setting EP4 FIFO Valid bit while NAKing an IN token. Bit 5 of REG[402Ch] indicates to the S1D13A0x controller when data in the endpoint 4 FIFO is ready to be transferred to the host computer. Changing the state of this bit at certain times may generate an error ...
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Page 2 Corrective Action: There are two software solutions for this occurrence. Disable USB Receiver before setting the EP4 FIFO Valid bit The first solution involves disabling the USB receiver to avoid responding to an EP4 IN packet. During the ...
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... S1D13A05 LCD/USB Companion Chip Programming Notes and Examples Document Number: X40A-G-003-04 Copyright © 2001, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13A05 X40A-G-003-04 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 2002/08/21 ...
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... Epson Research and Development Vancouver Design Center 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Identifying the S1D13A05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Display Buffer Location . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades 4.3 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades 4.4 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades ...
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... Programming the USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.1 Registers and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 10.1.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 10.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.2.1 GPIO Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 10.2.2 USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 10.3 Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 S1D13A05 X40A-G-003-04 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 2002/08/21 ...