GS1522 Gennum Corporation, GS1522 Datasheet

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... This device requires a single 5V supply and typically consumes less than 1000mW of power while driving two 75Ω cables. TEMPERATURE The GS1522 uses the GO1515 external VCO connected to the internal PLL circuitry to achieve ultra low noise PLL 0°C to 70°C performance. RESET ...

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... Typical Loop Bandwidth 1.485Gb/s Intrinsic Jitter Pseudo-random 23 PRBS (2 -1) (200kHz LBW) Pathological 23 PRBS (2 -1) (200kHz LBW) Pseudo-random (1.5 MHz LBW) Pathological (1.5 MHz LBW) GENNUM CORPORATION VALUE 5.5V V – 0.5 < V < 0 TBD TBD TBD 125°C 0°C ≤ T ≤ 70°C A -40°C ≤ T ≤ ...

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... PARAMETER CONDITIONS Positive Supply Voltage Operating Range Power (system power 5.00V, T=25° 5.00V, T=25°C CC Supply Current V = 5.25V, T=70° 5.00V, T=25°C CC SDO1 disabled V = 5.25V, 70°C CC SDO1 disabled V = 5.0V, 25°C CC GENNUM CORPORATION SYMBOL MIN TYP MAX ...

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... LFA 90 LBCONT 91 LFA_V CC3 V 95 EE3 SYNC_DETECT_DISABLE 100 NC 101 NC 102 NOTE: No Heat Sink Required GENNUM CORPORATION GS1522 TOP VIEW SDO1_EN 30 V EE2 29 V EE2 28 V EE2 27 V ...

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... TEST Test Pin . Test block output. Leave floating for normal operation. TTL Output Status Signal Output . Indicates when the GS1522 is phase locked to the incoming PCLK_IN clock signal. LOGIC HIGH indicates PLL is in Lock. LOGIC LOW indicates PLL is out of Lock. TTL Input Control Signal Input ...

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... DATA_IN[19:0] 106, 107, 110, 111, 112, 113, 114, 115, 118, 119, 122, 123, 124, 125, 126, 127, 128 GENNUM CORPORATION LEVEL TYPE TTL TEST Test Signal . Used for manufacturing test purposes only. This pin must be tied low for normal operation. Power Input Negative Supply ...

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... PD_V EE 50 VCO Fig. 1 VCO/VCO Input Circuit 10k 10k DM 85µA DFT_V EE Fig Output Circuit 20k 10k PLCAP 100µA PD_V Fig. 3 PLCAP/PLCAP Output Circuit GENNUM CORPORATION PD_V CC 5k 10k 40 31p VCO PD_V CC PD_V CC PLCAP LFS EE 7 LFA_V 500 LFA ...

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... All on-chip resistors have ±20% tolerance at room temperature. Fig. 7 PLL_LOCK Output Circuit PD_V 10k 30k A PD_V EE Fig. 8 IJI Output Circuit SDO SDO + - R SET CD_V EE Fig. 9 SDO/SDO Output Circuit GENNUM CORPORATION CC PLL_LOCK SYNC_DETECT_DISABLE EE Fig. 10 Data Input and SYNC_DETECT_DISABLE Circuit CC IJI PCLK_IN RESET 8 V CC3 2k BIAS 10k D0 - D19, V EE3 V ...

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... To disable these features, set the BYPASS pin (16) HIGH. 5. SLEW PHASE LOCK LOOP (S-PLL) An innovative feature of the GS1522 is the slew phase lock loop (S-PLL). When a step phase change is applied to the PLL, the output phase gains constant rate of change with respect to time ...

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... Fig. 14 PLL Characteristics 5.1. Phase Detector The phase detector portion of the slew PLL used in the GS1522 is a bi-level digital phase detector. It indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. When the phase detector is locked, the data transition edges are aligned to the falling edge of the clock ...

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... Kƒ x 500 x Ι /2. P 5.4. Phase Lock Loop Frequency Synthesis The GS1522 requires the HDTV parallel clock (74.25 or 74.25/1.001MHz) to synthesize a serial clock which is 20 times the parallel clock frequency (1.485MHz) using a phase locked loop (PLL). This serial clock is then used to strobe the output serial data. Figure 16 illustrates this operation ...

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... An accurate jitter peaking measurement of 0.1dB for the GS1522 requires the modulation source to have a constant amount of jitter modulation index (within 0.1dB or 1.2%) over the frequency range beyond the loop bandwidth. GENNUM CORPORATION It has been determined that for 282 ...

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... HIGH. The normalized filtered sample quadrature clock is 1.0. We chose a threshold of 0.66 to generate the phase lock signal. Because the threshold is lower than 1, it allows jitter to be greater than 0.5UI before the phase lock circuit reads it as “not phase locked”. GENNUM CORPORATION BW at 0.2 UI JITTER BW CCP2 MODULATION ...

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... DM signal. Figure 22 shows an example of such a situation. An HDTV SDI signal is modulated with a signal causing about 0.2UI jitter (Channel 1). The GS1522 receives this signal and locks to it. Figure 22 (Channel 2) shows the DM signal. Notice the wave shape of the DM signal, which is synchronous to the modulating signal ...

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... GENNUM CORPORATION 0.02 0.03 Admittances SET Fig. 24 Uncompensated Output Eye Waveform SET SET Fig. 25 Compensated Output Eye Waveform NOTE: Figures 24 and 25 show the waveforms on an oscilloscope using a 75Ω to 50Ω pad. ...

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... Tweak the layout until a return loss of 25dB is attained while the GS1522 is not mounted and L1 is shorted. When the device is mounted, use different inductors to match the parasitic capacitance of the IC. When the correct inductor is used, maximum return loss of 5MHz to 800MHz is achievable ...

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... DFT_V 88 EE LFA_V 89 LFA LFA 90 LBCONT LBCONT 91 CC LFA_V SYNC_DETECT_DISABLE 100 nc 101 nc 102 GENNUM CORPORATION LBCONT IJI SDO1_EN ...

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... The figures above show the recommended application circuit for the GS1522. The external VCO is the GO1515 and is specifically designed to be used with the GS1522. Figures 28 through 31 show an example PC board layout of Fig. 28 Top Layer of EB1522 PCB Layout ...

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... Fig. 30 Power Layer of EB1522 PCB Layout APPLICATION INFORMATION APPLICATION INFORMATION APPLICATION INFORMATION APPLICATION INFORMATION Please refer to the EBHDTX documentation for more detailed application and circuit information on using the GS1522 with the GS1501 and GS1511 Formatters. GENNUM CORPORATION Fig. 31 Bottom Layer of EB1522 PCB Layout 19 522 - ...

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... P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. 12 TYP 17.20 ±0.25 12.50 REF 14.0 ± ...