CMX969D5 MX-COM, Inc., CMX969D5 Datasheet - Page 25

• Manufacturer Part Number: CMX969D5
• Description: MOTIENT/ARDIS RD-LAP MDC4800 Modem
• Manufacturer: MX-COM, Inc.

MOTIENT
4.6.5.2
This bit reflects the availability of the Data Block Buffer and is cleared to '0' whenever a task other than NULL
or RESET is written to the Command Register.
In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem
when the modem is ready for the µC to write new data to the Data Block Buffer and the next task to the
Command Register.
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem
when it has completed a task and any data associated with that task has been placed into the Data Block
Buffer. The µC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register
4.6.5.3
In transmit mode, this bit signals ‘Interleave Buffer Empty’ and will be set to '1' - also setting the IRQ bit -
when less than two symbols remain in the Interleave Buffer. Any transmit task written to the modem after this
bit goes to '1' will be too late to avoid a gap in the transmit output signal.
In transmit mode this bit is also set to '1' by a RESET task or by a change of the Mode Register
PSAVE bits, but in these cases the IRQ bit will not be set.
In transmit mode this bit is cleared to '0' within one symbol time after a task other than NULL or RESET is
written to the Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid level (half-way between
'+1' and '-1') signal will be sent to the RRC filter.
In receive mode this bit is set to ‘1’ - also setting the IRQ bit - when the Autonomous Frame Sync circuit is
enabled (by setting b7 of the Command Register) and a received Frame Sync pattern is detected. The bit is
cleared to ‘0’ immediately after reading the Status Register. To avoid confusion this bit is not set when Frame
Sync is detected as part of a RD-LAP SFP task.
In receive mode this bit is also cleared to '0' by a RESET task or by a change of the Mode Register
ZP or PSAVE bits.
4.6.5.4
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB, RSID, R8B or R4S task
is written to the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the
Command Register or by changing the
In transmit mode this bit is '0'.
4.6.5.5
In receive mode this bit will be updated at the end of a SFP, RHB, RILB or RSID task (when BFREE goes
high) to reflect the result of the receive CRC check. '0' indicates that the CRC was received correctly, '1'
indicates an error. In transmit mode this bit will be '0'.
Note that this bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task, or by changing the
4.6.5.6
In receive mode this bit is set to '1' whenever an 'S' symbol or channel status bit (other than the 94
been received. In RD-LAP mode the µC may then read the value of the symbol from the SVAL field of the
Status Register. In MDC mode the value of the received channel status bit will be in bit 0 of the Status
Register.
In transmit mode this bit is set to '1' whenever an 'S' symbol or channel status bit (other than the 94
been transmitted.
The bit is cleared to '0' immediately after a read of the Status Register, by a RESET task or by changing the
¤ ¤ ¤ ¤ 2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
TX/
TX/
RX
RX
, ZP or PSAVE bits are changed.
, ZP or PSAVE bits of the Mode Register.
SM
/ARDIS
Status Register B6: BFREE - Data Block Buffer Free
Status Register B5: IBEMPTY - Interleave Buffer Empty /
AFSDET - Autonomous Frame Sync Detect
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
Status Register B3: CRCERR - CRC Checksum Error
Status Register B2: SRDY - 'S' Symbol Ready
SM
RD-LAP
www.mxcom.com Tel: [phone] 744 5050 Fax: [phone]
TM
MDC4800 Modem
TX/
RX
, ZP or PSAVE bits of the Mode Register.
25
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TX/
RX
, ZP or PSAVE bits of the Mode Register.
CMX969 Advance Information
Doc. # 20480211.002
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RX
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