CMX969 Consumer Microcircuits Limited, CMX969 Datasheet - Page 14

• Manufacturer Part Number: CMX969
• Description: RD-LAP/MDC4800/Motient/ARDIS4-Level FSK Packet Data Modem
• Manufacturer: Consumer Microcircuits Limited

RD-LAP/MDC4800 Motient/ARDIS
Mode Register B6: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
Mode Register B5: TXRXN - Tx/Rx Mode
Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into Receive mode.
Note that changing between receive and transmit modes will cancel any current task.
Mode Register B4: ZP - Zero Power
Setting this bit to ‘1’ removes power from all of the CMX969’s circuitry, including the Xtal oscillator, the Vbias
supply and the Tx o/p buffer. The µC interface will continue to operate except for the Command Register
which will not recognise or execute commands when ZP is ‘1’ as it relies on a clock source for correct
operation.
To obtain the lowest power consumption in Zero Power mode, the Mode Register TXRXN bit (B5) should be
set to 0 when the ZP bit (B4) is set to 1.
Mode Register B3: PSAVE - Powersave
When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx Symbol and
Clock extraction circuits and the Tx o/p buffer will be disabled, and the TxOp pin will be connected to Vbias
through a high value resistance. The Xtal Clock oscillator, Rx i/p amplifier and the µC interface logic will
continue to operate.
Setting the PSAVE bit to '0' when the ZP bit is ‘0’ restores power to all of the chip circuitry. Note that the
internal filters - and hence the TxOp pin in transmit mode - will take about 20 symbol-times to settle after the
PSAVE bit is taken from '1' to '0'.
Mode Register B2: SSIEN - 'S' Symbol IRQ Enable
In receive mode, setting this bit to '1' causes the IRQ bit of the status register to be set to '1' whenever a new
channel status 'S' symbol has been received. (The SRDY bit of the Status Register will also be set to '1' at the
same time, and the SVAL bits updated to reflect the received 'S' symbol.)
In transmit mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a 'S'
symbol or channel status bit has been transmitted. (The SRDY bit of the Status Register will also be set to '1'
at the same time.)
In MDC mode no interrupt is generated for the unused ‘94
Mode Register B1, 0: SSYM - 'S' Symbol To Be Transmitted
In transmit mode these two bits define the next 'S' symbol or channel status bit to be transmitted. These bits
have no effect in receive mode.
2001 Consumer Microcircuits Limited
B6
0
1
'+3 or +1'
'+3 or +1'
B1
'-3 or -1'
'-3 or -1'
Symbol
1
1
0
0
B0
1
0
0
1
Signal at TXOP
Above V
Above V
Below V
Below V
RD-LAP
‘+3’
‘+1’
‘-1’
‘-3’
14
BIAS
BIAS
BIAS
BIAS
th
bit’ in each block.
MDC
‘+1’
‘+1’
‘-1’
‘-1’
Signal at RXFB
Above V
Above V
Below V
Below V
BIAS
BIAS
BIAS
BIAS
CMX969
D/969/5