MB88346B-P Fujitsu Microelectronics, Inc., MB88346B-P Datasheet - Page 5

• Manufacturer Part Number: MB88346B-P
• Description: R-2r Type 8-bit D/A Converter With op Amp Output Buffers
• Manufacturer: Fujitsu Microelectronics, Inc.

MB88346B
FUNCTIONAL DESCRIPTION
OVERVIEW
The MB88346B is an R-2R resistor ladder type, 8-bit resolution digital-to-analog converter (DAC) device. The MB88346B has 12 channels of
D/A converters with operational amplifier output buffers. 8-bit digital data are loaded into internal data latches by individual DAC channel units.
The loaded digital data are converted into analog DC voltages through the internal D/A converter in max. 20 s settling time. And the analog
DC voltages source/sink the output current through the operational amplifier output buffers. For cascade connection, a serial data output is
provided.
DEVICE CONFIGURATION
As illustrated in BLOCK DIAGRAM, the MB88346B device is composed by the digital block (MCU interface) and analog block (D/A converter
with operational amplifier output buffers). The digital block consists of a 12-bit shift register, a 4-bit address decoder, and 12-channels of 8-bit
data latches. The analog block includes 12 channels of 8-bit D/A converters with operational amplifier output buffers connecting to the data
latches. For electrically stable operation the power supply and ground lines are separate between the digital block (MCU interface) and
operational amplifier output buffers, and analog block except operational amplifier output buffers.
DEVICE OPERATION
Figure 2 shows the input/output timing. A 12-bit address/data is serially input into the shift register through the DI pin synchronously with the
rising edge of CLK. The format of the shift register is shown in Figure 3. The lower 8 bits (D7 to D0) are data bits to be converted, and the
upper 4 bits are address bits (D11 to D8) to select a data latch to be written. A high level on the LD pin loads the address decoder with the 4-
bit address to select a data latch, and writes the 8-bit data into a selected data latch. Figure 4 shows the data latch address map, and Table,
address decoding. 8-bit data written into individual data latches are converted into analog DC voltages, dividing the supply voltage |V
-Vss|
DD
through R-2R resistor ladders of D/A converters. The operational amplifier output buffers at individual D/A converter outputs can source up to
1.0 mA of the output current. Figure 5 shows a configuration of the R-2R resistor ladder D/A converter with operational amplifier, and Table
3analog DC voltages corresponding to each digital data.
Figure 2 Input/Output Timing
CLK
MSB
LSB
D11
D10
D9
D8
D2
D1
D0
DI
LD
Previous Data
New Data
AOx
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