MB86615 Fujitsu Microelectronics, Inc., MB86615 Datasheet
MB86615
Related parts for MB86615
MB86615 Summary of contents
Page 1
... One built-in port plus a differential transceiver and comparator are provided to enable formation of networks in a 1394 cable environment. The MB86615 supports s100 data transfer speeds. By integrating the physical layer and link layer on one chip, The MB86615 is designed to reduce mounting area as well as power consumption. ...
Page 2
... MB86615 (Continued) • Built-in CSR’s to provide isochronous resource manager functions • 32-bit CRC generation and check functions • General purpose port for asynchronous transfer and control (16-bit MPU/DMA common bus) • Exclusive built-in ports for isochronous transfer (8-bit bus) • Built-in CRS’s and automatic processes to support DVC 1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending ...
Page 3
... D14 7 D13 8 D12 9 D11 10 D10 AD5 18 AD4 19 AD3 20 AD2 21 AD1 (FPT-100P-M05) MB86615 N.C. 72 N.C. 71 N. TPA 60 TPB 59 TPA ...
Page 4
... MB86615 2. FBGA-120 N. VCOIN DD SS N.C. ROI N.C. CHPO TP ROP DD SS BIAS AV AV TPB DD SS TPA TPB N.C. TPA N.C. N. N. N.C. N.C. N.C. N.C. AV TEST3 ID7 SS AV TEST2 V N. TEST1 N.C. V TEST4 TESTP XO DACK N. DREQ A2 SS ...
Page 5
... MB86615 I/O I/O I/O Pin Name Pin Name Pin Name — N. DREQ PMODE PMODE DACK — CTR CTR V DD — OCLK ...
Page 6
... MB86615 (Continued) NO. I/O 71 — 72 — 73 — 74 — 75 — 76 IU/O 77 IU/O 78 — 79 — 80 IU/O 81 IU/O 82 I/O 83 I/O 84 I/O 85 I/O 6 Pin Name NO. N.C. 86 N. TEST1 91 TEST2 TEST3 95 TEST4 96 ID7 97 ID6 98 ID5 99 ID4 100 I/O Pin Name I/O ID3 I/O ID2 I/O ID1 I/O ID0 — — ...
Page 7
... L12 — L11 O TPBIAS 67 K13 — K12 — K11 I/O TPB 70 J13 I/O TPA 71 J12 I/O TPB 72 J11 — N.C. MB86615 Pin Ball I/O Pin Name No. No. 73 H13 I/O TPA 74 H12 — H11 — G13 — N.C. 77 G12 — N.C. 78 G11 — F13 — ...
Page 8
... MB86615 (Continued) Pin Ball I/O Pin Name No. No. 109 A6 — 110 B6 I ICLK 111 C6 I IDIR 112 A5 O ILWRE 8 Pin Ball I/O Pin Name No. No. 113 B5 — N.C. 114 115 A4 O ICRCE 116 B4 I/O FP Pin Ball I/O Pin Name No. No. 117 C4 O TEST5 ...
Page 9
... FIFO buffer and asserted back if the FIFO buffer still contains any packet of data which has been received completely. loaded into the ISO-FIFO buffer at the rising edge of the ICLK signal. data from the ISO-FIFO buffer to the ID7 to ID0 pins. Data is then switched at the rising edge of the ICLK signal. MB86615 (Continued) 9 ...
Page 10
... Reception mode: Time stamp match detection signal output pin. 3. System Interface Pin name I Input pin for signals used by the MPU to select the MB86615 as an I/O device. Address input pins for internal register selection Valid only in non-multiplexed mode. If multiplexed mode is selected these pins should be fixed at ‘0’. ...
Page 11
... Input ‘1’ for multiplexed mode. TESTP O Test pin. Do not connect. TEST1 to TEST4 IU/O Test pin. Do not connect. TEST5 O Test pin. Do not connect. AV — Analog power supply DD AV — Analog ground SS V — Digital power supply DD V — Digital ground SS N.C. — Unused pin. Do not connect. MB86615 Function 11 ...
Page 12
... MB86615 BLOCK DIAGRAM IDIR ICLK ILWRE ID7 to ID0 IV ICRCE FP send-only CS (128 byte D15 to D6, D0 receive-only AD5 to AD1 (128 byte) RD (R/W) WR (DS) ALE INT DREQ DACK 12 ISO sending packet processing ISO LINK receiving layer packet control processing circuit ASYNC ASYNC sending FIFO ...
Page 13
... DVC registers and CSR. The built-in CSR provides isochronous resource manager functions. • PLL Circuit This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating clock and transfer clock signals. Reference oscillator frequency: 8.192 MHz. MB86615 13 ...
Page 14
... MB86615 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage* 1 Input voltage* 1 Output voltage* 1 Strage temperature 2 Operating temperature* Output current* 3 Overshoot Undershoot* *1: Voltage values are based on Vss = 0 V. *2: Not warranted for continuous operation. *3: Normal output current flow (Minimum maximum * less ...
Page 15
... Symbol Conditions I Driver disabled IC V Driver disabled SCH V Driver disabled SCZ V Driver disabled SCL V Driver disabled SD V Driver disabled SC MB86615 = + Value Unit Min. Max. 172 265 mV –0.81 0.44 mA — 1.665 2.015 + Value Unit Min ...
Page 16
... MB86615 1.3 System Interface, etc Parameter “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage Input pins Input leak current 3-state pin input Input pull-up resistance Power supply current 3 ...
Page 17
... DF Value Symbol Min. Typ. f 8.191992 8.192 C t — 1/fc CLF t 50 — CLCH t 50 — CLCL t — — — — CLF CLCL MB86615 Unit Max. 0.8 ns 0.8 ns 3.2 ns 3.2 ns Unit Max. 8.192008 MHz — ns — ns — ...
Page 18
... MB86615 2.3 System Reset Parameter Reset (RESET) “L” level pulse width RESET 18 Value Symbol Min tclf WRSL t WRSL Unit Max. — ns ...
Page 19
... RWSM t 10 RWHM t 15 ALE t 15 DWD t 40 DSM t 10 DWSM t 0 DWHM t 20 LWD CWSM t RWSM t t ALE DWD t AWHM Address MB86615 Value Unit Max. — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — CWHM t RWHM ...
Page 20
... MB86615 (2) 68-System Register Read Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time R/W setup time R/W hold time ALE “H” level pulse width ALE fall to DS fall time DS “L” level pulse width Data output definition time ...
Page 21
... Min AWS t 20 AWH t 20 CWS t 10 CWH t 20 RWS t 10 RWH DWS t 0 DWH t AWS t DS MB86615 Value Unit Max. — ns — ns — ns — ns — ns — ns — ns — ns — AWH t CWH t RWH t t DWS DWH Data ...
Page 22
... MB86615 (4) 68-Series Register Read Operation (non-multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time R/W setup time R/W hold time DS “L” level pulse width Data output definition time Data output disabled time R/W DS D15 to D6, D0 AD5 to AD1 22 Symbol Min ...
Page 23
... CWSM t 10 CWHM t 15 ALE t 15 DWD t 40 WRM t 40 DWSM t 0 DWHM t 20 LWD CWSM t t ALE DWD t AWSM AWHM Address MB86615 Value Unit Max. — ns — ns — ns — ns — ns — ns — ns — ns — ns — CWHM t LWD t WRM t t DWSM ...
Page 24
... MB86615 (6) 80-Series Register Read Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time ALE “H” level pulse width ALE fall to RD fall time RD “L” level pulse width Data output definition time Data output disabled time ...
Page 25
... D15 to D6, D0 AD5 to AD1 Symbol Min AWS t 20 AWH t 20 CWS t 10 CWH DWS t 0 DWH t AWS Address CWS t WR MB86615 Value Unit Max. — ns — ns — ns — ns — ns — ns — AWH t CWH t t DWS DWH Data 25 ...
Page 26
... MB86615 (8) 80-Series Register Read Operation (non-multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time RD “L” level pulse width Data output definition time Data output disabled time D15 to D6, D0 AD5 to AD1 (9) INT Signal Operation Parameter Interrupt read operation to INT signal negate ...
Page 27
... DAWH t 20 DRWS t 10 DRWH t 40 DDS t 30 DDSH t 30 DDWS t 0 DDWH DAWS DRWS t t DDS DDSH t t DDWS DDWH Data MB86615 Value Unit Max. — — ns — ns — ns — ns — ns — ns — ns — DHDL t DAWH t DRWH Data ...
Page 28
... MB86615 (2) 68-Series DMA Read Operation Parameter DREQ “H” to “L” DACK “H” to “L” DS DREQ setup time DACK hold time DACK R/W setup time R/W hold time DS “L” level pulse width DS “H” level pulse width Data output definition time ...
Page 29
... Value Symbol Min DHAL t — DHDL t 20 DAWS t 0 DAWH t 40 DWR t 30 DWRH t 30 DDWS t 0 DDWH t t DWR DWRH t t DDWS DDWH Data MB86615 Unit Max. — — ns — ns — ns — ns — ns — DHDL t DAWH Data 29 ...
Page 30
... MB86615 (4) 80-Series DMA Read Operation Parameter DREQ “H” to “L” DACK “H” to “L” RD DREQ setup time DACK hold time DACK RD “L” level pulse width RD “H” level pulse width Data output definition time Data output disabled time ...
Page 31
... Clock rise time Clock fall time t ICLH ICLK Value Symbol Min. — 62.5 ICLK t 20 ICLH t 20 ICLL t — ICR t — ICF t ICLK t t ICF ICR t ICLL MB86615 Unit Max. 16 MHz 250 ns — ns — ...
Page 32
... MB86615 2.6.2 Sending Operation (1) Start Sending Operation Parameter IDIR fall to ILWRE fall time ICLK rise to ILWRE fall time ILWRE fall to IV fall time IV setup time Data setup time Data hold time ICLK IDIR ILWRE IV ID7 to ID0 32 Symbol Min. t SDIR t SIDIR t ILIV t SIV ...
Page 33
... ICLK rise to ILWRE rise time IDIR rise to IDIR fall time ICLK IDIR ILWRE IV ID7 to ID0 N 1 Symbol Min HDIR t — DWR t — SWDIR t 250 DIRH t DWR t t HDIR DIRH MB86615 Value Unit Max. — ICLK 40 ns — SWDIR 33 ...
Page 34
... MB86615 (3) IV Temporary Negation in Sending Operation Parameter IV hold time Date setup time Data hold time ICLK IDIR ILWRE IV ID7 to ID0 Symbol Min. t HIV HIV Value Unit Max – ICLK 20 — — ...
Page 35
... FIFO buffer loads one packet of data after detection of the bus reset.) The ILWRE signal is asserted back when transmission of one packet of data to the 1394 bus is completed. Symbol Min. t — HWRL t t REMIV ICLK t — HWRH t HWRL t REMIV valid valid MB86615 Value Unit Max – ICLK HWRH ignore 35 ...
Page 36
... MB86615 (5) Switch to Transmission from Reception in Process Parameter IDIR fall to ILWRE rise time IDIR fall to ILWRE fall time ICLK IDIR ILWRE (6) FP Input Timing Parameter FP “L” level pulse width FP “H” level pulse width FP “H” detection to CTR value load FP 36 ...
Page 37
... The ICRCE signal is output when a CRC error is detected in receiving data. ICLK IDIR t WREH ILWRE IV ID7 to ID0 Hi Z ICRCE Value Symbol Min. t — WREH t 40 SIV t — — ERRL t SIV ERRL MB86615 Unit Max — ...
Page 38
... MB86615 (2) End Receiving Operation Parameter ICLK rise to ILWRE rise Data output disable time ILWRE negate time rise to ICRCE rise time* 2 *1: This device negates the ILWRE signal upon completion of reading each packet of data. *2: The ICRCE signal is asserted only when a CRC error is detected in data received. ...
Page 39
... Parameter IV rise to ICLK rise IV rise to ICRCE rise time IV fall to ICRCE fall time ICLK IDIR ILWRE IV ID7 to ID0 N 3 ICRCE Symbol Min HIV t — ERRH t — ERRL t HIV ERRH MB86615 Value Unit Max. — ERRL 39 ...
Page 40
... MB86615 (4) FP Signal Output Parameter IDIR fall to FP output enable FP “L” level pulse width Time stamp match detect to FP output IDIR t ZFP Value Symbol Min. t — ZFP t 600 FPW — — t FPW Unit Max 730 ...
Page 41
... ISO-FIFO control register has been set to “1.” Parameter IV rise to ILWRE rise ILWRE negate time ILWRE The ISO transmission/reception FIFO buffer is cleared while the ILWRE signal is negated. Symbol Min. t — CLR t — WREH t t CLR WREH MB86615 Value Unit Max ICLK ICLK 41 ...
Page 42
... Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary for AV/C (DVC) operation, and bank 2 contains CSR’s. In addition each bank has registers used in common for MB86615 device control. 1. Bank Common Registers The following registers can be accessed in any bank from bank 0 to bank 2. ...
Page 43
... Receiving ISO-channel setting register (0, 1) Receiving ISO-channel setting register (2, 3) (reserved) (reserved) (reserved) MB86615 Read operation Receiving ISO PKT header display register (high) Receiving ISO PKT header display register (low) Receiving ASYNC des ID setting register Receiving ASYNC PKT param ...
Page 44
... MB86615 3. Bank 1 Registers Bank 1 contains the registers required for AV/C (DVC) protocols. Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh). Address HEX ...
Page 45
... Write operation bus manager ID register (high) bus manager ID register (low) bandwidth available register (low) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) MB86615 Read operation 45 ...
Page 46
... MB86615 ORDERING INFORMATION Partnumber MB86615PFV MB86615PBT 46 Package 100-pin plastic LQFP (FPT-100P-M05) 120-pin plastic FBGA (BGA-120P-M01) Remarks ...
Page 47
... 120-Ø0.45±0.10 (120-Ø.018±.004) MB86615 Details of "A" part 0.15(.006) 0.15(.006) 0.15(.006)MAX 0.40(.016)MAX 0.10±0.10 (STAND OFF) (.004±.004) 0.50±0.20(.020±.008) 0~10˚ ...
Page 48
... MB86615 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division ...