TA235 ST Microelectronics, Inc., TA235 Datasheet - Page 2

• Manufacturer Part Number: TA235
• Description: Technical Article
• Manufacturer: ST Microelectronics, Inc.

TA 235
Figure 2. Firmware Hub Read Protocol
Figure 3. Firmware Hub Write Protocol
Firmware Hub Interface
The FWH Interface features:
It has an Input Clock (CLK) synchronized with the
33MHz PCI clock and a 3.3V Input/Output bus.
Figure 1 shows the pin description for FWH
interface mode.
There are two different protection modes designed
for the FWH interface. The hardware protection
has the Top Block Lock (TBL) that prevents the
Top Block from being changed, and the Write
Protect (WP) that prevents all the other blocks
from being changed.
2/6
a five Signal Communication Interface (FWH0-
FWH4) to support the Read and Write
operations,
five General Purpose Inputs (FGPI0-FGPI4) for
platform design flexibility,
four Identification Inputs (ID0-ID3) to address
up to 16 different memory devices,
a Register Based Block Locking and a
Hardware Block Protection for firmware
security.
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
START
1
1
IDSEL
IDSEL
1
1
ADDR
ADDR
7
7
MSIZE
MSIZE
1
1
Figure 4. Address/Address Multiplexed
Interface Configuration
A0-A10
DATA
TAR
2
RC
RP
2
W
IC
G
11
TAR
SYNC
2
3
M50FW040
V CC
V SS
SYNC
DATA
1
V PP
2
TAR
TAR
2
8
2
DQ0-
DQ7
RB
AI03441
AI03437
AI03796