MP1542 MPS, MP1542 Datasheet - Page 8

• Manufacturer Part Number: MP1542
• Description: Monolithic Power Systems
• Manufacturer: MPS

Compensation
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are f
and load resistance and f
compensation capacitor C3. The zero f
by the compensation capacitor C3 and the
compensation
determined by the equations:
Where R
error amplifier transconductance, and A
the error amplifier voltage gain.
The DC loop gain is:
Where V
There is also a right-half-plane zero (f
exists in continuous conduction mode (inductor
current does not drop to zero on each cycle)
step-up converters. The frequency of the right
half plane zero is:
Table
compensation components for different input
voltage, output voltage and capacitance of most
frequently used output ceramic capacitors.
Ceramic capacitors have extremely low ESR,
therefore the second compensation capacitor
(from COMP to GND) is not required.
01/05, Rev. 1.0
A
VDC
FB
1
LOAD
is the feedback regulation threshold.
=
f
f
1
RHPZ
lists
P
is the load resistance, G
f
5 .
f
2
P1
P
Z
1
1
=
×
resistor
set by the output capacitor C2
=
=
A
=
2
π
2
VEA
×
2
generally
×
×
V
×
π
C2
π
IN
×
π
×
×
G
2
C3
V
×
×
V
×
1
1
C3
EA
OUT
L
IN
R
×
×
R
R3.
LOAD
×
×
V
A
LOAD
2
R3
R
OUT
MPS Proprietary Information. © 2005 All Rights Reserved.
MP1542 – 700KHz/1.3MHz BOOST CONVERTER WITH A 2A SWITCH
VEA
P2
LOAD
Unauthorized Photocopy and Duplication Prohibited.
recommended
2
These
set by the
×
V
RHPZ
EA
FB
Z1
VEA
is the
is set
) that
are
is
For faster control loop and better transient
response,
recommended value in Table 1. Then slowly
increase the resistor R3 and check the load
step response on a bench to make sure the
ringing and overshoot on the output voltage at
the edge of the load steps is minimal. Finally,
the compensation needs to be checked by
calculating the DC loop gain and the crossover
frequency. The crossover frequency where the
loop gain drops to 0dB or a gain of 1 can be
obtained visually by placing a –20dB/decade
slope at each pole, and a +20dB/decade slope
at each zero. The crossover frequency should
be at least one decade below the frequency of
the right-half-plane zero at maximum output
load current to obtain high enough phase
margin for stability.
V
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
12
12
12
12
12
12
5
5
5
5
5
5
5
5
5
IN
Table 1—Component Selection
V
(V)
set
12
12
18
15
15
15
18
18
18
12
12
12
18
18
18
12
18
18
OUT
8
8
8
8
8
8
the
(µF)
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
C2
10
22
10
22
10
22
10
22
10
22
10
22
10
22
10
22
capacitor
INITIAL RELEASE
(kΩ)
5.1
5.1
R3
10
10
10
15
15
15
20
20
30
10
10
15
15
15
20
20
20
30
10
10
15
15
C3
to
(nF)
2.2
2.2
2.2
2.2
2.2
4.7
4.7
2.2
2.2
2.2
2.2
2.2
2.2
C3
1
1
1
1
1
1
1
1
1
1
1
the
8