MB86H20 Fujitsu, MB86H20 Datasheet

MB86H20

Manufacturer Part Number

MB86H20

Description

SmartMPEG

Manufacturer

Fujitsu

Datasheet

1.MB86H20.pdf (2 pages)

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INTRODUCTION:

This SmartMPEG is an integrated MPEG-2 set-

top-box decoder which includes the hardware extensions

required to support a low Bill of Material for Set-Top-

Boxes and IDTVs.

Highlights of the SmartMPEG include an ARC

RISC

demultiplexers with integrated DVB descramblers, a PAL/

NTSC/SECAM digital video encoder and a display

controller, which overlays up to four layers of graphic data.

A specially designed, shared SDRAM memory interface

for the CPU and MPEG decoder connects to a single

SDRAM device using either a 16 or 32-bit data bus

depending on customer bandwidth requirements. The

included universal processor interface allows simple

connection to FLASH, hard disk drives (IDE), Common

Interface and other asynchronous devices.

The SmartMPEG is part of Fujitsu’s MPEG

decoder family, and is the successor to the MB87L2250.

The SmartMPEG offers several advantages over

the MB87L2250, including support for 16/32-bit SDRAM

devices up to 128Mbytes, an integrated S/P-DIF interface,

DPLL, and internal audio DAC’s. This helps to reduce

product cost by eliminating the need for external

components. The SmartMPEG adds also DPLL

functionality, SECAM encoding, and two Smart-card

interface to former MPEG devices.

To help our customers achieve the shortest possible time-

to-market, the SmartMPEG comes with the Fujitsu

Driver Application Programming Interface (FAPI).

FAPI is a complete driver set, allowing fast and efficient

customer software design. In addition, FAPI is now the

standard

components, easing migration to future devices.

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

Product Profile

MB86H20

MPEG-2 Decoder for Set-Top-Boxes

CPU

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

programming

(@130.5MHz),

interface

two

TS3

intern

I-Cache

Power-

ARC@130.5MHz

Down

Par/Ser

TS1

DPLL

Tangent-A4

DVB Descramblers

TS Demultiplexers

for

transport

D-Cache

CTRL

IRQ

TS2

Par/Ser

Buffer Mgr

Watch-

Timers

Dog

Fujitsu

27.0MHz

(64Mbit … 1Gbit)

Shared Memory

SDRAM

SmartMPEG

Interface

Memory

Shared

NOR / NAND Flash

HDD/IDE

CTRL

16/32 bit

HDD / IDE / CI

Processor

Universal

Interface

stream

Chip Select

CTRL

MPEG-2 Video Decoder

MPEG Audio Decoder

S/P-DIF Output Unit

DVB

SmartMPEG Internal Bus @ 130.5MHz

Boot

ROM

(Dolby Dig. Bitstream)

I2S (Audio)

S/P-DIF

IR Rx

I2C

TXT Insertion

WSS / VPS

IRQ / I2C / 2 Smart Card

Resizing

Insertion

UART / IR In / IR Out

FEATURES

• MPEG2 video ISO/IEC 13818-2 (MP@ML...SP@ML)

• MPEG audio layer 1/2

• 32-bit RISC CPU (ARC Tangent A4 @130.5MHz)

• 4K I-cache, 2K D-cache

• Three timers / watchdog / power-down mode

• Shared memory interface (SDRAM, 16/32 bit data),

• Universal processor interface (IDE, NAND/NOR

• Two transport stream decoders (decoding/recording)

• Flexible MPEG video resizing (factor 1/16 to 2)

• Display controller with up to 4 true colour graphic or

• Flexible frame rate conversion (e.g. 50/60Hz)

• Flicker fixer for better on-screen text clarity

• Teletext / WSS / VPS / CC / VBID insertion

• PAL/NTSC/SECAM digital encoder

• RGB De-matrix (RGB or YCrCb output)

• Control of brightness, contrast and colour saturation of

• 5 video DAC’s @10bit for analogue video / audio O/P

• ITU-R 656 video input/output (shared with TS2 input)

• S/P DIF output for PCM/AC3/MPEG

• UART / 2 x Smart Card IF / I2C / GPIO / PWM Output

• 7-segment LED controller for 5 digits / KeyBoard mon.

• Infra Red receiver / transmitter

• On-chip DPLL, requiring only 27.0MHz crystal

• Bootable from NOR Flash or I2CPROM

• FPT-208P-M06 (LQFP-Package)

• Ambient Temperature Range (Std Pkg): 0

• Advanced Technology: Fujitsu CMOS Cx81 (0.18µm)

• 1.8 volt device with 3.3 volt I/O

• Power consumption: typ. 700mW (Standby: 100mW)

UART

IR Tx

64Mbit...1Gbit

FLASH & Common Interface)

including two DVB descrambler

CLUT layers (total 6 layers)

RGB and YCrCb output

(2 x 2 Layer)

Controller

CC/VBID

Insertion

Display

ITU-R656

2 Smart

GPIO

Card

Preliminary

GPIO / 7-Segment Ctrl

PWM / KeyBoard Mon

RGB De-Matrix

(PAL/NTSC/

Adjustable

Encoder

SECAM)

Digital

PWM

GPI

ITU-R656

7-Seg

CTRL

CVBS, YC, RGB

Output

GPO

DAC1

DAC2

DAC3

DAC4

DAC5

Analog O/P:

Audio R/L

November 2003

FME/MM/PP/1103

Edition 0.55

C to +70

Page 1 of 2

Related parts for MB86H20

MB86H20 Summary of contents

Page 1

... Product Profile MB86H20 MPEG-2 Decoder for Set-Top-Boxes INTRODUCTION: This SmartMPEG is an integrated MPEG-2 set- top-box decoder which includes the hardware extensions required to support a low Bill of Material for Set-Top- Boxes and IDTVs. Highlights of the SmartMPEG include an ARC RISC CPU (@130.5MHz), two transport ...

Page 2

... Copyright © 2003 Fujitsu Microelectronics Europe GmbH Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before November 2003 Edition 0.55 MB86H20 MPEG-2 Decoder for Set-Top-Boxes Asia Tel: +65 6281 0770 Fujitsu Microelectronics Asia ...

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