MB81EDS256445 Fujitsu, MB81EDS256445 Datasheet
MB81EDS256445
Related parts for MB81EDS256445
MB81EDS256445 Summary of contents
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... MB81EDS256445 ■ DESCRIPTION The Fujitsu MB81EDS256445 is a CMOS Fast Cycle Random Access Memory (FCRAM*) with Low Power Double Data Rate (LPDDR) SDRAM Interface containing 268,435,456 storages accessible in a 64-bit format. MB81EDS256445 is suited for consumer application requiring high data band width with low power consumption. ...
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... MB81EDS256445 ■ PIN DESCRIPTIONS Symbol Type CK, CK Input CKE Input CS Input RAS Input CAS Input WE Input BA[1:0] Input A[11:0] Input AP(A10) Input DM[7: Input DQ[63: I/O DQS[7: I Supply DDQ Supply SSQ DM0, DM1, DM2, DM3, DM4, DM5, DM6 and DM7 correspond to DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56]. ...
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... The combination of RAS, CAS, and WE input in conjunction with rising edge of the CK define the command for device operation. Refer to the “■COMMAND TRUTH TABLE”. 5. Bank Address Inputs (BA0, BA1) BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. DS05-11456- MB81EDS256445 ...
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... MB81EDS256445 6. Address Inputs (A0 to A11) Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. Total twenty address input signals are required to decode such a matrix. Row Address (RA) is input from A0 to A11 and Column Address (CA) is input from A0 to A7. Row addresses are latched with ACTIVE (ACT or MACT) com- mands, and Column addresses and Auto Precharge (AP) bit are latched with Read (READ or READA) or Write command (WRIT or WRITA) ...
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... BLOCK DIAGRAM CK CLOCK CK BUFFER CKE A[11:0] ADDRESS BUFFER BA[1:0] CS RAS COMMAND DECODER CAS WE DM[7:0] I/O DQS[7:0] BUFFER DQ[63:0] DS05-11456-1E MB81EDS256445 To each block BURST COUNTROLLER ADDRESS COUNTROLLER MODE REGISTER MEMORY CORE READ CONTROLLER AMP V DDQ SSQ Y CONTROLLER Bank3 Bank2 Bank1 Bank0 MEMORY CELL ARRAY (1 M bit × ...
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... MB81EDS256445 ■ SIMPLIFIED STATE DIAGRAM DEEP DPD POWER DOWN MODE REGISTER SET BST WRIT WRITE WRITA WRITE WITH AUTO PRECHARGE PRE POWER ON POWER APPLIED Note: “■SIMPLIFIED STATE DIAGRAM” is based on the single bank operation. State transition of multi bank operation are not described in all detail. ...
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... The Mode Register is used to configure the type of device function among optional features. This device has 2 Mode Registers, Mode Register and Extended Mode Register. Mode Registers can be programmed by MODE REGISER SET (MRS) command. Refer to the “Mode Register Table” in “■FUNCTIONAL DESCRIPTION”. DS05-11456-1E MB81EDS256445 ) and start clock. Attempt to maintain DDQ 7 ...
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... MB81EDS256445 Mode Register Table Mode Register Extended Mode Register Pre Driver Strength ...
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... A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A D-E-F-0-1-2-3-4-5-6-7-8-9-A-B E-F-0-1-2-3-4-5-6-7-8-9-A-B-C F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E MB81EDS256445 (Hexadecimal ...
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... MB81EDS256445 4. CAS Latency (CL) CAS Latency (CL) is the delay between READ command being registered and first read data becoming available during read operation. First read data will be valid after (CL-1) × t command being latched. 5. Driver Strength (DS) Driver Strength (DS adjust the driver strength of data output. ...
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... STATE DIAGRAM”. *7: MRS command can be issued after all banks have been precharged and all DQ are in High-Z. Mode Register and Extended Mode Register are selected through BA input. Mode Register and Extended Mode Register must be set by MRS command after power up. DS05-11456-1E MB81EDS256445 CS RAS CAS WE ...
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... MB81EDS256445 2) CKE Command Truth Table Command SELF REFRESH ENTRY * 1 SELF REFRESH EXIT * 2 POWER DOWN ENTRY * 1 POWER DOWN EXIT DEEP POWER DOWN ENTRY * 1 DEEP POWER DOWN EXIT Note Valid can be either *1: SELF and DPD commands can be issued after all banks have been precharged and all DQ are in High-Z. ...
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... BANK ACTIVE DS05-11456-1E MB81EDS256445 Address Command X X DESL H X NOP L X BST H BA, CA, AP READ/READA L BA, CA, AP WRIT/WRITA H BA, RA ACT L BA, AP PRE/PALL H X REF L MODE MRS X X DESL ...
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... MB81EDS256445 Current State CS RAS CAS WE READ WRITE Address Command X X DESL H X NOP L X BST ...
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... WRITE WITH AUTO PRE CHARGE DS05-11456-1E MB81EDS256445 Address Command X X DESL H X NOP L X BST H BA, CA, AP READ/READA L BA, CA, AP WRIT/WRITA H BA, RA ACT L BA, AP PRE/PALL H X REF L MODE MRS X ...
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... MB81EDS256445 Current State CS RAS CAS WE Write Recovering Precharging Address Command X X DESL H X NOP ...
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... Illegal to bank in the specified state. Command entry may be legal depending on the state of bank selected by BA. *2: NOP to bank in precharging or in idle state. Bank in active state may be precharged depending on BA. *3: Illegal if any bank is not idle. *4: MRS command should be issued on condition that all DQ are in High-Z. *5: Requires appropriate DM masking. DS05-11456-1E MB81EDS256445 Address Command X X DESL ...
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... MB81EDS256445 ■ BANK OPERATION COMMAND TABLE Minimum clock latency or delay time for single bank operation MRS ⎯ MRD MRD ACT ⎯ ⎯ t RCD READ ⎯ ⎯ 1 *1, *2 BL/2 READA BL/2 ⎯ WRIT ⎯ ⎯ *1, *2 BL/2 BL/2 WRITA ⎯ DAL ...
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... WTR WTR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ t REFC ⎯ ⎯ ⎯ ⎯ t REFC MB81EDS256445 MRD MRD MRD MRD ⎯ ⎯ RAS *4 ⎯ ⎯ BL/2 BL/2 BL ...
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... MB81EDS256445 ■ COMMAND DESCRIPTION 1. DESELECT (DESL) When CS is High at the CK rising edge, all input signals are neglected. Internal operation such as burst cycle is held OPERATION (NOP) NOP disables address and data input and internal operation such as burst cycle is held. 3. BANK ACTIVE (ACT) ACT activates the bank selected by BA and latch the row address through A0 to A11 ...
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... Data Output Timing CK CK Command READ t (Min.) AC DQS DQ t (Max.) AC DQS DQ Read Preamble and Postamble @ Command READ DQS DQ DS05-11456-1E MB81EDS256445 CAS Latency NOP t t DQSCK DQSCK odd even t t DQSQ DQSQ DQSCK t DQSCK ...
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... MB81EDS256445 5. READ with Auto Precharge (READA) READA commands can be issued by READ command with AP (A10 Auto precharge is a feature which precharge the activated bank after the completion of burst read operation. The t ACTIVE (ACT) command to the internal precharge which starts after BL/2 from READA command. READ with Auto precharge operation should not be interrupted by subsequent READ, READA, WRITE, WRITEA commands ...
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... DQSH DQSL t DSS Q Q even odd MB81EDS256445 ). WPST t t DSH DSS Q odd DSS DSH Mask Q odd ...
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... MB81EDS256445 Write Preamble and Postamble CK CK Command WRITE t WPRES DQS t WPRE WRITE with Auto Precharge (WRITA) WRITA commands can be issued by WRIT command with AP (A10 Auto precharge is a feature which precharge the activated bank after the completion of burst write operation. The t ...
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... PALL command. A10 determines whether one or all banks are RP Tj Max ( °C) t (ms) REF + 105 16 + 125 4 after CKE brought High, and then the NO OPERATION command IS . Refer to the “(15) Self Refresh Entry and Exit” in “■TIMING DIAGRAMS” IS MB81EDS256445 period. CKE should be held REFC period to avoid the REFC 25 ...
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... MB81EDS256445 17. DEEP POWER DOWN ENTRY (DPD) DEEP POWER DOWN ENTRY (DPD) commands to drive the device in Deep Power Down mode which is the lowest power consumption but all stored data and the contents of mode registers will be lost. During Deep Power Down state, all inputs signals except for CKE are “don't care” and all DQs and DQS will be in High-Z. Deep Power Down mode must be entered on conditions that all DQs are in High-Z and all banks are in IDLE state ...
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... No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. ■ CAPACITANCE Parameter Input Capacitance, Except for DM Input Capacitance for DM I/O Capacitance DS05-11456-1E MB81EDS256445 Symbol Rating V ,V -0.5 to +2.3 DD DDQ ...
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... MB81EDS256445 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Output High Voltage V I OH(DC) OH Output Low Voltage V I OL(DC ≤ V Input Leakage I LI Current All other pins not under test = 0 V Output Leakage 0 V ≤ Current Operating One Bank t RC Active-Precharge I addresses inputs are SWITCHING; ...
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... After power on, initialization following power-up timing is required. DC characteristics are guaranteed after the initialization. • I depends on the output termination or load condition, clock cycle rate, signal clocking rate. DD The specified values are obtained with the output open condition. DS05-11456-1E MB81EDS256445 Condition , ...
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... MB81EDS256445 2. AC Characteristics Parameter DQ Output Access Time from CK/CK (t DQS Output Access Time from CK/CK * Clock High Level Width * 3 Clock Low Level Width * 3 4 Delay between CK and Clock Cycle Time and DM Input Setup Time DQ and DM Input Hold Time DQ and DM Input Pulse Width ...
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... The data valid window depends DQSQ and t must be equal or greater than specified minimum t RAS RP (AC) min and V (AC) max MB81EDS256445 *1, *2 Value Unit Min. Max. 37 8000 ns ⎯ 59.2 ns ⎯ 100 ns ⎯ ⎯ ⎯ ...
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... MB81EDS256445 3. Measurement Condition of AC Characteristics V DD 0.1 μ × 0 Ω DEVICE OUT UNDER TEST 10 pF DS05-11456-1E ...
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... TIMING DIAGRAMS (1) Read* (Assuming CKE H CS RAS CAS Address RA DM DQS DQ t RCD ACT * : RA = Row Address Bank Address Column Address Auto Precharge DS05-11456-1E MB81EDS256445 RAS t RC READ PRE ACT Don’ ...
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... MB81EDS256445 (2) Read to Read* 1 (Assuming CKE H CS RAS CAS Address DQS DQ t RCD ACT ACT READ * Bank 0 Bank 1 Bank * Row Address Bank Address Column Address Auto Precharge *2: Previous burst read can be interrupted by subsequent burst read. ...
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... RA = Row Address Bank Address Column Address Auto Precharge *2: Burst read operation can be terminated by PRE command. All DQ pins become High-Z after CL from PRE command. DS05-11456- RCD PRE ACT MB81EDS256445 RAS READ PRE Don’t care 35 ...
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... MB81EDS256445 (4) Read with Auto-Precharge * 1 (Assuming CKE H CS RAS CAS Address RA DM DQS DQ t RCD ACT * Row Address Bank Address Column Address Auto Precharge *2: Internal precharge operation starts after BL/2 from READA command. t *3: Next ACT command can be issued after BL ...
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... Address DQS DQ t RCD ACT WRIT * Row Address Bank Address Column Address Auto Precharge *2: Burst write operation should not be terminated by PRE command. PRE can be issued after WRIT command. DS05-11456-1E MB81EDS256445 RAS t RC ...
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... MB81EDS256445 (6) Write to Write * 1 (Assuming CKE H CS RAS CAS Address DQS DQ t RCD ACT ACT WRIT Bank 0 Bank 1 Bank Row Address Bank Address Column Address Auto Precharge *2 : Previous burst write can be interrupted by subsequent burst write. ...
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... Address DQS DQ t RCD ACT WRITA * Row Address Bank Address Column Address Auto Precharge *2 : Next ACT command can be issued after DS05-11456-1E MB81EDS256445 BL/2 t RAS t RC Precharge start (Min) from WRITA command. t DAL ...
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... MB81EDS256445 (8) Read to Write * 1 (Assuming CKE CS RAS CAS Address DQS DQ t RCD ACT READ * Row Address Bank Address Column Address Auto Precharge *2 : WRIT command can be issued after CL + BL/2 after READ command ...
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... Address DQS DQ t RCD ACT READ * Row Address Bank Address Column Address Auto Precharge *2 : WRIT command can be issued after CL from burst read termination by BST command. DS05-11456-1E MB81EDS256445 1 (Assuming BST WRIT D5 ...
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... MB81EDS256445 (10) Write to Read * 1 (Assuming CKE H CS RAS CAS Address DQS DQ t RCD ACT WRIT * Row Address Bank Address Column Address Auto Precharge *2 : READ command can be issued after ...
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... DM DQS DQ t RCD ACT WRIT * Row Address Bank Address Column Address Auto Precharge *2 : The data input after 1 clock from BST command will be masked READ command can be issued after DS05-11456-1E MB81EDS256445 (Assuming Masked *2 by BST ...
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... MB81EDS256445 (12) Write to Read with DM Mask * CK CK CKE H CS RAS CAS Address DQS DQ t RCD ACT WRIT * Row Address Bank Address Column Address Auto Precharge * must be High during t from last pair of input data. WTR 44 1 (Assuming CL= ...
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... CAS Address DQS DQ t RCD ACT WRIT * Row Address Bank Address Column Address Auto Precharge *2 : When DM is registered High, the corresponding data will be masked. DS05-11456-1E MB81EDS256445 Masked * RAS t RC PRE BA RA ...
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... MB81EDS256445 (14) Auto Refresh * CKE H CS RAS CAS Address DM DQS REF *2 PALL * Row Address Bank Address Auto Precharge *2 : All banks must be precharged prior to the AUTO REFRESH command (REF Either NOP or DESL command should be asserted during ACT or MRS or REF command should be asserted after t ...
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... SELF REFRESH EXIT (SELFX) command can be latched at the CK rising edge Either NOP or DESL command can be used during CKE should be held High during t DS05-11456- SELFX period. REFC period after SELFX command. REFC MB81EDS256445 High-Z High-Z REFC *4,*5 t ACT Don’t care 47 ...
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... MB81EDS256445 (16) Mode Register Set CKE H CS RAS CAS Address DM DQS PALL REF * Row Address Bank Address Auto Precharge *2 : MODE REGISTER SET (MRS) command must be asserted after all banks have been precharged and all DQ are in High-Z. 48 Code ...
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... DM DQS DQ PALL Row Address Bank Address Auto Precharge * command can be issued after all DQ are in High- ACT command can be issued after 1 clock from POWER DOWN EXIT (PDX) command. DS05-11456- MB81EDS256445 High-Z High-Z PDX *3 ACT Don’t care ...
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... MB81EDS256445 (18) Deep Power Down Entry CKE CS RAS CAS Address DM DQS PALL * : DEEP POWER DOWN ENTRY (DPD) Command can be issued after all banks have been precharged and all DQ are in High-Z. 50 DPD High-Z High-Z Don’t care DS05-11456-1E ...
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... CKE CS RAS CAS Address DM DQS DQ 300 µs *2 DPDX PALL * Row Address Bank Address Auto Precharge *2: Power up initialization procedure must be performed after DPDX command. DS05-11456-1E MB81EDS256445 Code Code Code Code Code Code REFC REFC MRD REF MRS EMRS ...
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... MB81EDS256445 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www ...