MB15F03SL Fujitsu Media Devices, MB15F03SL Datasheet - Page 10
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MB15F03SL
Manufacturer Part Number
MB15F03SL
Description
Dual Serial Input PLL Frequency Synthesizer
Manufacturer
Fujitsu Media Devices
Datasheet
1.MB15F03SL.pdf
(25 pages)
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10
MB15F03SL
Table.4 Brinary 11-bit Programmable Counter Data Setting
Table.5 Brinary 7-bit Swallow Counter Data Setting
Table.6 Prescaler Data Setting
Table.7 Phase Comparator Phase Switching Data Setting
Table.8 LD/fout Output Select Data Setting
Prescaler
divide ratio
VCO polarity
Note: Divide ratio less than 3 is prohibited.
Note: Divide ratio (A) range = 0 to 127
Note: Z = High-impedance
fr > fp
fr = fp
fr < fp
Divide
Divide
LDS
2047
ratio
ratio
127
H
(N)
(N)
L
3
4
0
1
Depending upon the VCO and LPF polarity, FC bit should be set.
11
FC
N
A
0
0
1
7
0
0
1
RF-PLL
IF-PLL
IF, RE
(1)
H
Z
L
10
fout (fr
N
A
= H
0
0
1
6
0
0
1
LD/fout output signal
Do
IF/RF
N
A
9
0
0
1
5
0
0
1
IF, RF
LD signal
SW = “H”
, fp
64/65
FC
8/9
IF/RF
N
A
8
0
0
1
4
0
0
1
IF, RE
(2)
H
Z
) signals
L
= L
N
A
7
0
0
1
3
0
0
1
SW = “L”
128/129
N
A
16/17
6
0
0
1
2
0
0
1
N
A
5
0
0
1
1
0
1
1
VCO Output
Frequency
N
4
0
0
1
N
3
0
1
1
N
2
1
0
1
LPF Output Voltage
N
1
1
0
1
(1)
(2)