MB15F03L Fujitsu Media Devices, MB15F03L Datasheet - Page 12

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MB15F03L

Manufacturer Part Number
MB15F03L
Description
Dual Serial Input PLL Frequency Synthesizer
Manufacturer
Fujitsu Media Devices
Datasheet

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12
MB15F03L
Note: Phase error detection range = 2 to +2
PHASE DETECTOR OUTPUT WAVEFORM
Pulses on Do
LD output becomes low when phase error is t
LD output becomes high when phase error is t
t
WU
Do
Do
and t
IF/RF
IF/RF
fr
fp
LD
(FC bit = High)
(FC bit = Low)
LD Output Logic Table
IF/RF
IF/RF
Locking state / Power saving state
Locking state / Power saving state
Unlocking state
Unlocking state
WL
depend on OSCin input frequency as follows.
IF/RF
IF–PLL section
t
t
WU
WL
signals are output to prevent dead zone.
Z
Z
< 8/fosc: i.e. t
> 4/fosc: i.e. t
t
WU
H
WL
WU
> 312.5ns when foscin = 12.8 MHz
< 625.0ns when foscin = 12.8 MHz
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Unlocking state
WU
WL
or more.
or less and continues to be so for three cycles or more.
t
WL
RF–PLL section
L
LD output
H
L
L
L

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