MB15E03L Fujitsu Media Devices, MB15E03L Datasheet - Page 7

• Manufacturer Part Number: MB15E03L
• Description: Single Serial Input PLL Frequency Synthesizer On-Chip 1.2 GHz Prescaler
• Manufacturer: Fujitsu Media Devices

1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Shift Register Configuration
VCO
FUNCTION DESCRIPTIONS
= [(M x N) + A] x f
Control bit (CNT)
f
N
A
f
R
M
VCO
OSC
Programmable Reference Counter
CNT : Control bit
R1 to R14: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
SW : Divide ratio setting bit for the prescaler (64/65 or 128/129)
FC
LDS : LD/fout signal select bit
Note: Start data input with MSB first
H
L
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
: Preset divide ratio of modules prescaler (64 or 128)
(LSB)
: Phase control bit for the phase comparator
C
N
1
T
R
1
2
OSC
R
3
2
R (A < N)
17 bit latch (for the programmable reference divider)
18 bit latch (for the programmable divider)
R
3
4
R
5
4
R
5
6
(Data Flow)
R
7
6
R
8
7
Destination of serial data
R
8
9
10
R
9
10
11
R
12
11
R
A
13
12
127)
R
14
13
R
15
14
R
SW
16
MB15E03L
17
FC
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
(MSB)
LDS
18
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