MB15A01 Fujitsu Microelectronics, MB15A01 Datasheet - Page 8

• Manufacturer Part Number: MB15A01
• Description: Bi-cmos 1.1 GHZ PLL Frequency Synthesizer
• Manufacturer: Fujitsu Microelectronics

8
(2) Divide Ratio of Programmable Divider
The programmable divider consists of a 19-bit shift register, an 18-bit latch, 7-bit swallow counter, and an 11-bit
programmable counter. Serial data is made up of the following 19 bits:
(3) Serial Data Input Timing
• 7-bit swallow counter divide ratio
S1 to S7: Swallow counter divide ratio setting bits (Divide ration of 0 to 127)
S8 to S18: Programmable counter divide ration setting bits (Divide ration of 16 to 2047)
C: Control bit (Set it to “L”)
Note: Start data input with MSB first.
Divide ratio
A
0
1
•
Clock
Data
LE
S
7
0
0
•
t
Note: Serial data is fetched at the rise of each clock pulse.
1
S
1
, t
4
Swallow counter divide ratio
S
>100 ns, t
6
0
0
•
MSB
Control bit
LSB
S
2
S
5
0
0
•
t
1
S
3
setting bits
(Set value: 0 to 127) Note: The divide ratio must not be less than 16. (Set value: 16 to 2047)
2
S
4
0
0
•
>1000 nw, t
S
4
S
3
0
0
•
S
5
S
2
0
0
•
3
S
6
>300 ns, t
S
1
0
1
•
S
7
• 11-bit programmable counter divide ratio
Divide ratio
S
5
8
>800 ns
t
2
Programmable counter divide ration setting bits
16
17
N
•
S
9
10
S
18
S
0
0
•
11
S
17
S
0
0
•
t
3
12
S
16
S
0
0
•
13
S
LSB
15
S
0
0
•
14
S
14
S
0
0
•
C: Control bit
15
S
13
S
1
1
•
16
S
t
12
4
S
0
MSB
0
•
t
17
5
S
11
S
0
0
•
18
S
10
S
0
0
•
MB15A01
S
9
0
0
•
S
8
0
1
•