MB1501 Fujitsu, MB1501 Datasheet - Page 4

• Manufacturer Part Number: MB1501
• Description: SERIAL INPUT PLL FREQUENCY SYNTHESIZER
• Manufacturer: Fujitsu

MB1501
MB1501H
MB1501L
4
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using Data pin, Clock pin and LE pin, The 15-bit programmable reference divider and 18-bit programmable
divider are controlled respectively.
On rising edge of the clock shifts one bit of the data into the internal shift registers.
When load enable (LE) is high level (or open), data stored in shift resisters is transferred to 15-bit latch or 18-bit latch depending upon
the control bit level.
Control data “H” ; Data is transferred into 15-bit latch.
Control data “L” ; Data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.
SW: Divide ratio of prescaler setting bit.
S
C: Control bit (Control bit is set to high.)
1
Last data input
to S
14
SW=“H” : 64
SW=“L” : 128
: Divide ratio of programmable reference counter setting bits (8 to 16383)
Divide ratio less than 8 is prohibited.
Divide ratio R: 8 to 16383
C
Divide
16383
ratio
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
R
8
9
S
1
14
S
0
0
1
S
2
Control bit
LSB
Divide ratio of programmable reference counter setting bits
13
S
1
0
S
0
3
12
S
0
0
1
S
4
11
S
0
0
1
S
5
10
S
0
0
1
S
6
Divide ratio of prescaler setting bit
Data input
S
9
0
0
1
S
7
S
8
0
0
1
S
8
S
7
0
0
1
S
9
10
S
0
0
1
6
S
11
S
5
0
0
1
S
12
S
4
1
1
1
S
MSB
13
S
0
0
1
3
S
14
S
2
0
0
1
S
SW
S
1
0
1
1
First data input