MCD212 Motorola, MCD212 Datasheet
MCD212
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MCD212 Summary of contents
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... Video Decoder and System Controller (with JTAG) Advance Information MCD212 Coming through loud and clear. Order this document by MCD212/D Rev. 0 ...
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... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MCD212/D* MCD212/D ...
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... BLOCK DIAGRAM 1.4 DIFFERENCES BETWEEN THE MCD211 AND THE MCD212 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... CURSOR POSITION REGISTER hCE CURSOR CONTROL REGISTER hCF CURSOR PATTERN REGISTER hC0–hD7 REGION CONTROL REGISTER 0–7 hC8 BACKDROP COLOR REGISTER hD9, hDA MOSAIC PIXEL HOLD FACTOR REGISTER hDB–hDC WEIGHT FACTOR REGISTER MCD212 4–1 4–2 4–4 4–5 4–5 5–1 5– ...
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... MCD212 5–19 5– ...
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... SECTION 12 PACKAGE DIMENSIONS APPENDIX MCD212 9– 9– 9– 9– ...
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... MCD212 Page No. ...
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... MCD212 Page No. 8– ...
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... MCD212 Page No. ...
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... MCD212 Page No. ...
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... MCD212 Page No. 9– ...
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... MCD212 MOTOROLA ...
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... The Video Decoder and System Controller with JTAG (VDSC/JTAG CMOS device integrating a 680X0 family system controller and video graphics decoder, see Figure 1–1 below. The MCD212 is a programmable, multi–scan video device that can function as either a master or a slave functionally equivalent to the MCD211 with the addition of JTAG testing. The MCD212 is a drop– ...
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... Special Effects via Weight Control, Priority Control, etc. Dynamic Programmable Registers and CLUT Reload in Retrace Period Digital RGB Output (8 Bits per Component) Synchro Generator for 50 and 60 Hz Scan Synchronization with External Video General: CMOS Technology 160–pin Quad Flat Pack Plastic Package 1–2 MCD212 MOTOROLA ...
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... JTAG testing has been added for automated board testing. The additional pins required to do this were V SS pins on the MCD211. Hence, the MCD212 can be put in place of an MCD211 and will function identically. The functionality of the R/W, LDS, UDS, A1 – A22, RAS pins have been en- hanced ...
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... This pin must be pulled up externally. BERR O Bus Error output. Active low, three–state. Asserted, when enabled, by the VDSC watchdog timer circuit if UDS or LDS is still asserted at the end of the time–out period. This pin must be pulled up externally. MOTOROLA PIN DESCRIPTION MCD212 2 2–1 ...
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... Vertical Synchronization. Active low. In master mode, this output is used as vertical synchronization signal for monitor. In slave TV mode it becomes a vertical synchronization input. Horizontal Synchronization. Active low. This output is used as a horizontal synchronization signal. Composite synchronization. Active low. This output is used as a composite synchronization signal. MCD212 MOTOROLA ...
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... CLK/2 clock output. Frequency is CLK frequency divided by 2. Inverse of CLK2 Power supply pins (5 V Power and signal ground pins. NOTE: All the pins are TTL compatible, except for CLK and RSTIN, which use CMOS levels. MOTOROLA internal pull–up. MCD212 2–3 ...
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... CLK, RSTIN :D0 – D15, RSTOUT, HALT, BERR, INT, MD0 – MD15, MA0 – MA9, LWR, UWR, R0 – R7, G0 – G7, B0 – B7, BLANK, CSYNC, HSYNC, VSYNC, VSD, CLK2, CLK2 :CSIO, CSROM :RAS, CAS1, CAS2 MCD212 MOTOROLA ...
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... CM2, IC2, DC2 DDR1: MF1, MF2, FT1, FT2 DDR2: MF1, MF2, FT1, FT2 MOTOROLA SYSTEM CONTROL t 100 ms bits 10, 11, 18 (plane A and B off, external video disabled) bit 23 (cursor disabled) bits (black backdrop) MCD212 3 1 VIDEO LINE 3–1 ...
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... Counter). The SSP and PC must be located at address h400000 and h400004 which are decoded during the swapping. Address are normally decoded afterwards. RTSIN U/LDS ADDRESS ACCESS TYPE Figure 3–3. Memory Swapping Timing Chart 3– ROM ROM ROM ROM MCD212 PC ROM ROM OR RAM MOTOROLA ...
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... Channel 1 internal registers Table 3–2. DTACK Delay for ROM DD DD1 DD2 CLK Cycles NOTE: Access to the SYSTEM I/O device (CSIO pin) is not acknowledged by the VDSC but by the addressed device. MCD212 3–3 ...
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... The IT1 bit and IT2 bit are reset after the CPU reads the CSR2R register. The INT pin is inactive when both IT1 and IT2 are reset (see equation above). 3–4 NO DTACK t 1 VIDEO LINE Figure 3–4. Bus Error Timing MCD212 READ CSR2R MOTOROLA ...
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... The selection between one or two banks is done by fixing the CAS1 and CAS2 pins to a logical level during reset. CAS1 corresponds to bank 1 and CAS2 corresponds to bank 2. See Table 4–1 for the address map of the DRAM banks. No DTACK is generated for addresses outside a certain configura- tion. MOTOROLA DRAM CONTROL MCD212 4 4–1 ...
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... NEXT DISPLAY PERIOD 16 CYCLES CH#2 SYS. CH#1 SYS. CH#2 Figure 4–1. DRAM Access MCD212 bank 1 bank 1 bank 2 bank 1 bank 1 bank 1 bank 2 bank 2 bank 2 bank 2 bank 1 bank 1 bank 2 bank 1 bank 1 bank 1 bank 2 bank 2 bank 2 bank 2 SYS. ...
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... Next is the DCA time if it has been enabled. The number of pixel periods of the DCA is programmed in the DCR register, with bytes) being the maximum. The rest of the video line time is then available as free–run time. MOTOROLA FREE–RUN RF DCA VIDEO LINE Figure 4–2. DRAM Cycles MCD212 VIDEO FIELD VERT. RES 4–3 ...
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... CAS1 asserted if validated and A18 = 0, A19 = 0, A20 = 0, A22 = 0 CAS2 asserted if validated and A18 = 1, A19 = 0, A20 = 0, A22 = 0 CAS1 asserted if validated and A20 = 0, A22 = 0 CAS2 asserted if validated and A20 = 1, A22 = 0 MCD212 COL COL COL Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö ...
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... D0 – – – – – RAS RAS RAS RAS CAS/OE CAS/OE CAS/OE CAS/OE MCD212 CASX Bank 2 DRAM 6 DRAM 7 DRAM 8 D0 – – – – – – RAS RAS ...
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... D0 – D15 MA0 – MA8 A0 – – A8 LWR LW LW UWR UW UW RAS RAS RAS CAS1 CAS/OE CAS2 CAS/OE MCD212 Bank 2 DRAM 6 DRAM 7 DRAM 8 D0 – – – – – – RAS RAS RAS ...
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... The field rate is twice the frame rate (60 Hz for NTSC and 50 Hz for PAL). Although each frame is made up of 525/625 lines, only 480/560 are visible on the screen. MOTOROLA IMAGE DISPLAY CONTROL BACKGROUND/EXTERNAL VIDEO GRAPHICS PLANE B CURSOR PLANE GRAPHICS PLANE A MCD212 5 5–1 ...
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... DOUBLE RESOLUTION DOUBLE RESOLUTION (PIXEL PAIRS) Table 5–2. Horizontal Resolution Pixels/Line Active Line Active Line ( 360 720 51.4 384 768 51.2/50.84 360 720 48/47.67 MCD212 240 240 280 (SINGLE PIXELS) Display Display System NTSC Monitor PAL/NTSC TV PAL/NTSC TV MOTOROLA ...
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... Non–interlace mode. One image is composed of one field. Interlace mode. One image is composed of two fields. IMAGE LINE 2 LINE 4 LINE 6 LINE N ODD FIELD + EVEN FIELD Frame Duration Image (ms) Frequency (Hz 15.3 50 15.3 60 MCD212 LINE 1 LINE 2 LINE 3 LINE 4 LINE 5 LINE 6 LINE N–1 LINE N = TOTAL IMAGE Display Type PAL PAL NTSC 5–3 ...
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... P = Vertical Sync Width Figure 5–5. VSYNC and BLANK Timing 5– CLK = CLK = 30 MHz 30 MHz 30.2097 MHz 30 2097 MHz ( 64.0 63.56 51.2 50.84 10.7 10.59 4 2.13 2.12 9 4.8 4.77 4 2.13 2.12 9 4.8 4. MCD212 CLK = CLK = MHz 30 MHz 30 2097 MHz 30.2097 MHz (Cycles 120 64.0 63.56 90 48.0 47.67 23 12.3 12.18 7 3.7 4.77 9 4.8 4.77 4 2.13 2. ...
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... Hz ( Even Field ( 312.5 312.5 240 280 240 46 26.5 46.5 6 26.5 2.5 2.5 2.5 P 311 312 261 262 MCD212 ( Odd Field Odd Field Even Field Even Field ( ( 262.5 262.5 240 240 18 18.5 4 5–5 ...
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... 524 525 262 263 264 265 Table 5–8. ICA Pointer Addresses Interlace Odd Field Non–Interlace ( h400 h400 h200400 h200400 MCD212 4 5 316 317 318 4 5 266 267 268 Even Field ( h404 h200404 MOTOROLA ...
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... When IC and DC are set to 1, the number of possible DCA fetches can be limited by the line retrace duration as indicated in the following tables. MOTOROLA ICA2/DCA2 Modes ICA1 DCA1 DE IC2 DC2 Yes Yes Yes MCD212 ICA2 DCA2 No No Yes No Yes Yes No No 5–7 ...
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... RELOAD VSR and Reload the VSR register and the video address STOP counter with the specified pointer and stop the control fetches as STOP instruction. INTERRUPT Set IT bit in CSR register. RELOAD DISPLAY MF1 d = MF2 e = FT1 PARAMETERS f = FT2 MCD212 DCA2 (in bytes ...
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... RELOAD VSR and Reload the VSR register and the video address STOP counter with the specified pointer and stop the control fetches as STOP instruction. INTERRUPT Set IT bit in CSR register. RELOAD DISPLAY MF1 d = MF2 e = FT1 PARAMETERS f = FT2 MCD212 5–9 ...
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... Mosaic Pixel Hold for Plane A DA Mosaic Pixel Hold for Plane B DB Weight Factor for Plane A DC Weight Factor for Plane Reserved — — — MCD212 — — MOTOROLA ...
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... MCD212 00 – – – – — — — — ...
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... Region Flag 1 or Color Key = False — — — — — — — — — MCD212 — — — TA3 TA2 TA1 TA0 Pixel is Transparent if — — ...
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... — — — — B7 MCD212 — — — — — — — ...
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... — — Figure 5–10. Cursor Position MCD212 MOTOROLA ...
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... Half–brightness magenta Half–brightness yellow Half–brightness white Black Blue Green Cyan Red Magenta Yellow White MCD212 — — — — Cursor Color 5–15 ...
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... CP15 AD 0 HEX F HEX MCD212 CP0 ...
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... Plane Reset Region Flag and Change Weight of Plane Set Region Flag and Change Weight of Plane — — — — — — — — — MCD212 — — — 5–17 ...
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... MCD212 Color of Background — — ...
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... N.B.: The explanation above concerns normal resolution display. With double resolution display all the widths must be doubled. MOTOROLA Horizontal Resolution Bitmap Width ST CM (pixels 360 0 1 720 1 0 360 1 1 720 0 0 384 0 1 768 1 0 360 1 1 720 MCD212 (bytes) 360 360 384 384 384 384 360 360 5–19 ...
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... Figure 5–12. VDSC in Slave Mode with an External PLL for Clock Generation Figure 5–13. VDSC in Slave Mode with an External Clock 5–20 Synchro Mode HSYNC CSYNC Master Out Out Slave TV Out Out EXT. VIDEO HSYNC SUBSYSTEM EXTERNAL PLL HSYNC VDSC EXT. VIDEO HSYNC VSYNC SUBSYSTEM VDSC CLK MCD212 VSYNC Out In MOTOROLA ...
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... Run–length 1 1 Mosaic NOTE: File type of display 1 is indicated in DDR1 register. Table 6–2. File Type of Display Display 1 File Type 0 x Bitmap 1 0 Run–length 1 1 Mosaic NOTE: File type of display 2 is indicated in DDR2 register. MCD212 6 6–1 ...
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... MEMORY DATA BUS MD15 – MD0 2ND NIBBLE 3RD NIBBLE 4TH NIBBLE BIT BIT BIT BIT BIT BIT PIXEL 2 PIXEL 3 PIXEL NUMBER OF IDENTICAL PIXELS (8 BITS MCD212 BIT MOTOROLA ...
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... CLUT N = NUMBER OF IDENTICAL PIXEL PAIRS (8 BITS MF1 MF2 Mosaic Factor NOTE: Bits indicated in DDR1 register Mosaic Factor NOTE: Bits indicated in DDR2 register. MCD212 0 6–3 ...
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... Tables 6–5 and 6–6). Table 6–5. Output Modes of Channel NOTE: Bits indicated in DCR1 register. Table 6–6. Output Modes of Channel NOTE: Bits indicated in DCR1 register. 6–4 Bits/Pixel Frequency 4 CLK/2 Bits/Pixel Frequency 4 CLK/2 MCD212 Resolution Double Resolution Double MOTOROLA ...
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... YUV decoding by only coding the difference between adjacent pixels rather than their absolute value; this is the delta. This difference is coded in 4 bits, using a non–uniform 16–level fixed quantizer. The VDSC executes the opposite operation, using the values in Table 7–1. MOTOROLA REAL-TIME DECODER MCD212 7 7–1 ...
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... DYUV decoding of coded pixel–data entering via channel 1 results in plane A and DYUV decoding of coded pixel–data entering via channel 2 results in plane B. 7–2 Table 7–1. Dequantizer Input Output 128 9 177 10 212 11 229 12 240 13 247 14 252 15 255 MCD212 MOTOROLA ...
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... CLUT 11 BANK CLUT 10 BANK 2 0 CHANNEL 1 PLANE A 63 CLUT 01 BANK CLUT 00 BANK Figure 7–2. CLUT Organization MCD212 READ (DECODING) CLUT7 CLUT4 127 CHANNEL 2 PLANE B OR CHANNEL 1 PLANE A 15 PLANE A/CH 127 CHANNEL 1 PLANE A 15 PLANE A/CH 7–3 ...
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... B2 B1 MSB Figure 7–4. Data Structure of RGB555 Input and Output Pixel 7– LSB MCD212 1 0 LSB 1 0 LSB X X LSB MOTOROLA 0 ...
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... CLUT7 0 Normal CLUT4 1 Double DYUV 0 Normal Coding Method CM1 Resolution OFF x x CLUT7 0 Normal CLUT4 1 Double DYUV 0 Normal RGB555 0 Normal Plane A CLUT8 CLUT7+7 CLUT7 CLUT4 MCD212 DYUV 7–5 ...
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... Blue Yellow Green Magenta Cyan Red Red Cyan Magenta Green Yellow Blue White Black MCD212 ...
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... N–1 pixels, where N is the pixel hold factor. This produces a mosaic–type effect on the image. See Figure 8–1 for an example. BEFORE PIXEL HOLD: P0 AFTER PIXEL HOLD (n = 3): P0 Figure 8–1. Pixel Hold Example for MOTOROLA VISUAL EFFECTS MCD212 8 8–1 ...
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... CONTROL REGISTER HORIZONTAL POSITION CONSTRAINT: X4 < X5 < X6 < RF0/ RF0/ RF0/ RF0/ RF0/ RF0/ RF1 RF1 RF1 RF1 RF1 RF1 MCD212 RF0 RF0/ RF0/ RF1 RF1 X6 X7 MOTOROLA ...
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... VSA is delayed one CLK2 clock cycle to counteract for a delay caused by a clocked DAC. VSD and VSA are active if enabled by the EV–bit of the “image coding method register” and when the backdrop is shown. MOTOROLA BACKGROUND/EXTERNAL VIDEO GRAPHICS PLANE B CURSOR PLANE GRAPHICS PLANE A Figure 8–5. Plane Order MCD212 8–3 ...
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... During horizontal and vertical blanking of the video a constant level is set on each component. For 50 Hz display this level is 16 and for 60 Hz display 0. 8–4 VDSC BACKDROP CURSOR + MUX MUX AB (0 255) BD CUR VSD VSA MCD212 EXTERNAL VIDEO ANALOG SWITCH DAC MOTOROLA ...
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... Display Decoder Register 1 Write DCA Pointer 1 Write Status Register 2 Read Control Register 2 Write Display Command Register 2 Write Video Start Register 2 Write Display Decoder Register 2 Write DCA Pointer 2 Write MCD212 9 h4FFFF1 h4FFFF0 h4FFFF2 h4FFFF4 h4FFFF8 h4FFFFA h4FFFE1 h4FFFE0 h4FFFE2 h4FFFE4 h4FFFE8 h4FFFEA 9–1 ...
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... DD2 — — TD Table 9–4. DTACK Delay DD DD1 DD2 CLK Cycles MCD212 IT1 IT2 ...
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... for the odd frame and 0 for the even frame. MOTOROLA — — — — — — — PA — — — — MCD212 — — — — — 0 — 9–3 ...
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... Mode) This bit is used to select the scan mode. 9– — — — — — IT1 IT2 IC1 DC1 — — A21 Table 9–9. Crystal Frequency CF Frequency in MHz 30, 30.2097 MCD212 A20 A19 A18 A17 A16 MOTOROLA ...
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... DC2 — — A21 Table 9–14. Channel 2 Color Mode CM2 Bits/Pixel Pixel Frequency 0 8 CLK CLK/2 Table 9–15. ICA1/DCA1 Enable IC2 DC2 ICA2 DCA2 Yes Yes Yes MCD212 A20 A19 A18 A17 A16 9–5 ...
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... FT1 FT2 Display File Type 0 x Bitmap 1 0 Run–length 1 1 Mosaic MF2 FT1 FT2 — — A21 A20 MCD212 A19 A18 A17 A16 A19 A18 A17 A16 MOTOROLA ...
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... FT1 FT2 Display File Type 0 x Bitmap 1 0 Run–length 1 1 Mosaic A10 A10 MCD212 : 9–7 ...
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... Table 9–25. Display Control Pointer 2 — Write, 4FFFEA A15 A14 A13 A12 A11 9– A10 A10 MCD212 — — — — MOTOROLA ...
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... MD9 122 A6 91 MD8 123 A5 92 MD7 124 MD6 125 A4 94 MD5 126 127 128 MCD212 10 PIN LIST Function Pin Function MD4 129 B3 MD3 130 V DD DTACKSEL 131 132 B5 MD2 133 B6 MD1 134 B7 MD0 135 ...
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... NOTE: Pin differences between the MCD211 and MCD212 are denoted with *. 10–2 MCD212 160 QFP TOP VIEW Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö ...
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... Operating Temperature Storage Temperature Test Conditions MOTOROLA ELECTRICAL SPECIFICATION Symbol Min Max Unit V DD – 0 – – — — 1200 mW T opr stg – 150 C MCD212 11 11–1 ...
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... – – out Parameter MCD212 Min Max Unit — 220 mA 0 — — 2.0 — ...
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... Pin 99 – High 32 ns (max) advance (68340/341–25) Timing of DTACK for ROM accesses is unchanged. 3. The delay d is the delay mentioned in the Delay Times Table and depends on the CLK frequency and the programmed value DD, DD1, DD2. MOTOROLA Parameter MCD212 Min Max Unit Note ...
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... U i Units 375 445 370 440 ns 110 175 105 170 ns 175 240 170 235 ns 240 310 235 305 ns 310 375 305 370 ns MCD212 Min Max Unit Note 25 — — — — — — — — ...
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... CLK 2 CLK2 CLK2 CLK2 CLK2 OE VIDEO* VSD VSA * Video: R0 – R7, G0 – G7, B0 – B7, VSYNC, HSYNC, BLANK MOTOROLA Figure 11–1. Clock Timing Figure 11–2. Video Timing MCD212 8 9 11–5 ...
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... Figure 11–3. CPU Read Cycle Timing A1 – A22 R – D15 U/LDS DTACK Figure 11–4. CPU Write Cycle Timing U/LDS CSROM CSIO DTACK FOR ROM 11– 26a Figure 11–5. System Timing MCD212 MOTOROLA ...
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... MOTOROLA CH#1/CH COL ROW COL COL Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö 55 Figure 11–6. DRAM Timing MCD212 COL COL 64 11–7 ...
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... MCD212 MOTOROLA ...
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... The VDSC is a surface mounting component and is housed in a 160–pin Plastic Quad Flat Package (QFP). MOTOROLA PACKAGE DIMENSIONS MCD212 12 12–1 ...
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... INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR Q PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MCD212 P -A,B,D- DETAIL BASE METAL D 0.13 (0.005 – ...
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... A.1 DELTA YUV ENCODING The MCD212 does not do the encoding of any image but this section is included as an informational reference to the process of image coding using the delta YUV (DYUV) process. Natural images are particularly well suited to DYUV encoding since there is usually little difference in the color or intensity of adjacent pixels ...
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... Y component is calculated based on the difference from the last calculated value and the desired value (the U and V are skipped): h7 next the delta for all components is calculated: and so on for the rest of the pixels: In the MCD212, the data is reconstructed as follows: The first pixel is given by the absolute value: 16,128,128 A–2 Code ...
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... The second is calculated using the output difference column from the table above: 20,127,137 Then the rest are calculated in the same way: 99 Therefore the data for the seven pixels would be stored on disk as follows (in hex): h10,h80,h80,hF2,h37,hDD,h48,h99,h89 MOTOROLA 90,118,153 218 139,39,25 60 MCD212 A–3 ...
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... A–4 MCD212 MOTOROLA ...