P12C508 Microchip Technology, P12C508 Datasheet - Page 19

• Manufacturer Part Number: P12C508
• Description: 8-Pin / 8-Bit CMOS Microcontroller
• Manufacturer: Microchip Technology

5.0
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF GPIO,W) always read the
I/O pins independent of the pin’s input/output modes.
On RESET, all I/O ports are defined as input (inputs
are at hi-impedance) since the I/O control registers are
all set. GP0 and GP1 can be programmed in software
with weak pull-ups.
5.1
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not set.
5.2
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see
Section 4.4.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 5-1:
Address
N/A
N/A
03H
06h
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
Note:
1996 Microchip Technology Inc.
I/O PORT
GPIO
TRIS Register
q = see tables in Section 7.7 for possible values.
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
TRIS
OPTION
STATUS GPWUF
GPIO
Name
SUMMARY OF PORT REGISTERS
I/O control registers
GPWU
Bit 7
—
GPPU
Bit 6
—
—
T0CS T0SE PSA PS2 PS1 PS0
Bit 5
GP5
PA0
Advance Information
Bit 4
GP4
TO
Bit 3
GP3
PD
Bit 2 Bit 1 Bit 0
GP2
Z
5.3
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output
operations. For input operations these ports are non-
latching. Any input must be present until read by an
input instruction (e.g., MOVF GPIO,W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
FIGURE 5-1:
Note 1: I/O pins have protection diodes to V
Data
Bus
WR
Port
W
Reg
TRIS ‘f’
GP1 GP0
DC
I/O Interfacing
C
D
D
CK
CK
Reset
Data
Latch
TRIS
Latch
--11 1111
1111 1111
0001 1xxx
--xx xxxx
Power-On
Value on
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Reset
Q
Q
Q
Q
PIC12C5XX
RD Port
WDT Reset
MCLR and
--11 1111
1111 1111
000q quuu
--uu uuuu
Value on
DS40139A-page 19
V
V
P
N
DD
SS
DD
Wake-up on
Pin Change
--11 1111
1111 1111
100q quuu
--uu uuuu
Value on
and V
I/O
pin
SS
.
(1)