FM24C64B Ramtron, FM24C64B Datasheet
FM24C64B
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FM24C64B Summary of contents
Page 1
... The FM24C64B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C64B is available in an industry standard 8-pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40° ...
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... Latch Serial to Parallel Converter Control Logic Figure 1. FM24C64B Block Diagram Pin Description Address 2-0: These pins are used to select one devices of the same type on the same two-wire bus. To select the device, the address value on the three pins must match the corresponding bits contained in the device address. The address pins are pulled down internally ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C64B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... If the receiver acknowledges the last byte, this will cause the FM24C64B to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24C64B can begin. For a read operation, the FM24C64B will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C64B will transfer the next sequential byte ...
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... Current Address & Sequential Read The FM24C64B uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation ...
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... Therefore, endurance cycles are applied for each read or write cycle. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C64B, a row is 64 bits wide. Every 8-byte boundary marks Rev. 1.3 Feb. 2011 set ...
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... IL 1 (min -0.3V and V , other inputs Stop command issued Does not apply to WP, A2-A0 pins FM24C64B Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55° 125°C 260° C 4kV 1.25kV 200V MSL-1 Typ Max Units Notes 5.0 5.5 ...
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... DD Parameter Max -40°C to +85° 4.5V to 5.5V unless otherwise specified min) to First Access (Start condition) DD min) DD waveform. DD FM24C64B Min Max Min Max Units 0 400 0 1000 kHz 1.3 0.6 µs 0.6 0.4 µs 0.9 0.55 µs 1.3 0.5 µs 0.6 0.25 µs 0.6 0.25 µ ...
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... 0 HIGH BUF t AA Stop Start t t HD:STA t SU:STO Stop Start Start Min FM24C64B Equivalent AC Load Circuit 5.5V 1700 Ω Output 100 LOW 1/fSCL t HD:DAT t SU:DAT t DH Acknowledge t HD:DAT t SU:DAT AA Acknowledge Max Units Notes - ...
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... RICYYWW Rev. 1.3 Feb. 2011 Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C64B, “Green” SOIC package, Year 2010, Work Week 47 FM24C64B-G A00002G1 RIC1047 FM24C64B Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Revision History Revision 1.0 11/10/2010 1.1 12/20/2010 1.2 2/7/2011 1.3 2/15/2011 Rev. 1.3 Feb. 2011 Date Summary Initial Release Changed V (max Added ESD ratings. Changed t and t spec limits FM24C64B +0.3V Datasheet pdf - http://www.DataSheet4U.net/ ...