FM24C04C Ramtron, FM24C04C Datasheet
FM24C04C
Related parts for FM24C04C
FM24C04C Summary of contents
Page 1
... No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM24C04C is capable of 12 supporting 10 read/write cycles million times more write cycles than EEPROM ...
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... Schmitt trigger input for improved noise immunity. Write Protect: When WP is high, the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down. No connect Supply Voltage Ground FM24C04C FRAM Array 8 Data Latch Page ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C04C due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... FM24C04C to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. Slave Address The first byte that the FM24C04C expects after a start condition is the slave address ...
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... After all address information has been transmitted, data transfer between the bus master and the FM24C04C can begin. For a read operation the FM24C04C will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded ...
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... Each time the bus master acknowledges a byte, FM24C04C should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24C04C Rev. 1.1 June 2011 Start Address & Data S Slave Address ...
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... Therefore, endurance cycles are applied for each read or write cycle. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C04C, a row is 64 bits wide. Every 8-byte boundary marks Rev. 1.1 June 2011 ...
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... IL 1 (min -0.3V and V , other inputs Stop command issued Does not apply to WP, A1, A2 pins FM24C04C Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55 125C 260 C 3kV 1.25kV 100V MSL-1 Typ Max Units 5.0 5.5 V ...
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... DD Parameter Max min -40C to +85 4.5V to 5.5V unless otherwise specified min) to First Access (Start condition) DD min) DD waveform. DD FM24C04C Min Max Min Max Units 0 400 0 1000 kHz s 1.3 0.6 s 0.6 0.4 s 0.9 0.55 s 1.3 0.5 s 0.6 0.25 s 0.6 ...
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... HIGH 1/fSCL t BUF t AA Stop Start t HD:DAT t t SU:DAT HD:STA t SU:STO Stop Start Min FM24C04C Equivalent AC Load Circuit 5.5V 1700 Output 100 LOW t HD:DAT t SU:DAT t DH Acknowledge t AA Acknowledge Max Units Notes - Years - Years ...
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... Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C04C, “Green”/RoHS SOIC package, Year 2010, Work Week 49 FM24C04C-G A00002G1 RIC1049 FM24C04C Recommended PCB Footprint 7.70 3.70 2.00 0.65 1.27 0.25 0.50 0. 0.40 1.27 Page ...
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... Revision History Revision 1.0 5/20/2011 1.1 6/30/2011 Rev. 1.1 June 2011 Date Summary Initial Release Added ESD ratings. FM24C04C Page Datasheet pdf - http://www.DataSheet4U.net/ ...