CM106-L+ C-Media Electronics, CM106-L+ Datasheet - Page 25

• Manufacturer Part Number: CM106-L+
• Description: USB Audio I/O Controller
• Manufacturer: C-Media Electronics

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CM106F+/L+ contains eight 16-bit DACs. The DACs are implemented in two-stage resister
ladder architecture. With 2X interpolator in logic block, these DACs are indeed operated at two
time of sample rate. The playback stream from USB host is in signed 16-bit binary.
CM106F+/L+’s logic block converts the data to unsigned format, and adds 64 as a fixed offset.
The converted data to DAC input is then in unsigned 17-bit binary. The 2X interpolator, and fixed
offset value added upon playback stream could improve SNR.
CM106F+/L+ contain two 16-bit ADCs. The ADCs are implemented in Sigma-Delta architecture.
In addition to the default digital low pass filter, CM106F+/L+ provides an alternate one that could
improve SNR further. A larger ADC input swing (4.0Vp-p) is also available. Refer to the internal
register section for more information.
To meet suspend current specification of USB, CM106 F+/L+ turns off most blocks when entering
suspend. The only two exception are power-on-reset and regulator.
To meet unconfigured current specification of USB, CM106 F+/L+ provides a control signal
PDSW to turn off external components. PDSW would be active when USB host does not
configure CM106 F+/L+. PDSW would also be active when CM106 F+/L+ is suspended. If serial
EEPROM is exist, notice that it should not be powered off anyway because it contains Vendor ID
and Product ID which should be returned to USB host before CM106 F+/L+ is configured.
The value of two input pin PWRSEL and PWRSEL1 (for CM106-F+ only) would affect
configuration descriptor. If users declare the device as bus-power and high-power, and it is
attached to a bus-power hub, USB host would not configure the device because the power
budget is over.
Date: 08/19/2005
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6.4 DAC
6.5 ADC
6.6 POWER MANAGEMENT
High End 8CH DAC and 2CH ADC Integrated Solution
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CM106-F+/L+
Version： 1.01