MSC23CV26457D-XXBS8 OKI electronic componets, MSC23CV26457D-XXBS8 Datasheet - Page 10

• Manufacturer Part Number: MSC23CV26457D-XXBS8
• Description: DYNAMIC RAM MODULE
• Manufacturer: OKI electronic componets

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Notes: 1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles
10. t
12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
11. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE
Semiconductor
2. The AC characteristics assume t
3. V
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF.
5. Operation within the t
6. Operation within the t
7. t
8. t
9. t
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
measured between V
The output timing reference levels are V
t
the access time is controlled by t
t
the access time is controlled by t
circuit condition and are not referenced to output voltage levels.
sheet as electrical characteristics only. If t
data out will remain open circuit (high impedance) throughout the entire cycle. If t
data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
then the condition of the data out (at access time) is indeterminate.
leading edge in an /OE control write cycle, or a read modify write cycle.
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin
will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low levels. The test
mode is cleared and the memory device returned to its normal operating state by performing a /RAS
only refresh cycle or a /CAS before /RAS refresh cycle.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
RCD
RAD
CEZ
CEZ
RCH
WCS
IH
t
RWD
(Min.) and V
(Max.), t
(Max.) is specified as a reference point only. If t
(Max.) is specified as a reference point only. If t
, t
or t
or t
CWD
(Min.), t
REZ
RRH
, t
must be satisfied for open circuit condition.
must be satisfied for a read cycle.
RWD
REZ
AWD
(Max.), t
IL
, t
(Max.) are reference levels for measuring input timing signals. Transition times (t
AWD
t
AWD
IH
RCD
RAD
and t
and V
WEZ
(Max.) limit ensures that t
(Min.) and t
(Max.) limit ensures that t
(Max.) and t
CPWD
IL
.
are not restrictive operating parameters. They are included in the data
T
CAC
AA
= 2ns.
.
.
CPWD
OEZ
OH
WCS
(Max.) define the time at which the output achieves the open
= 2.0V and V
t
CPWD
t
WCS
(Min.), then the cycle is a read modify write cycle and
RAC
RAC
RCD
RAD
(Min.), then the cycle is an early write cycle and the
(Max.) can be met.
(Max.) can be met.
is greater than the specified t
is greater than the specified t
OL
= 0.8V.
CWD
RCD
RAD
(Max.) limit, then
(Max.) limit, then
t
CWD
MSC23CV26457D
(Min.), t
T
) are
RWD