STPC STMicroelectronics, STPC Datasheet - Page 2

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STPC

Manufacturer Part Number
STPC
Description
PC Compatible Embeded Microprocessor
Manufacturer
STMicroelectronics
Datasheet

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STPC CONSUMER
To check if your memory device is supported by
the STPC, please refer to Table 9-3 in the
Programming Manual.
2/51
X86 Processor core
Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
Can access up to 4GBytes of external
memory.
8KByte unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
Clock core speeds up to of 100 MHz.
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 3.3V operation.
DRAM Controller
Integrated system memory and graphic frame
memory.
Supports up to 128 MBytes system memory
in 4 banks and down to as little as 2Mbytes.
Supports 4MB, 8MB, 16MB, 32MB single-
sided and double-sided DRAM SIMMs.
Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.
Four 4-word read buffers for PCI masters.
Supports Fast Page Mode & EDO DRAM.
Programmable timing for DRAM parameters
including CAS pulse width, CAS pre-charge
time and RAS to CAS delay.
60, 70, 80 & 100ns DRAM speeds.
Memory hole between 1 MByte & 8 MByte
supported for PCI/ISA busses.
Hidden refresh.
Graphics Engine
64-bit windows accelerator.
Backward compatibility to SVGA standards.
Hardware acceleration for text, bitblts,
transparent blts and fills.
Up to 64 x 64 bit graphics hardware cursor.
Up to 4MB long linear frame buffer.
8-, 16-, and 24-bit pixels.
Drivers for Windows and other operating
systems.
Issue 1.2
VGA Controller
Integrated 135MHz triple RAMDAC allowing
for 1280 x 1024 x 75Hz display.
Requires external frequency synthesizer and
reference sources.
8-, 16-, 24-bit pixels.
Interlaced or non-interlaced output.
Video Input port
Accepts video inputs in CCIR 601/656 or
ITU-R 601/656, and stream decoding.
Optional 2:1 decimator
Stores captured video in off setting area of
the onboard frame buffer.
Video pass through to the onboard PAL/
NTSC encoder for full screen video images.
HSYNC and B/T generation or lock onto
external video timing source.
Video Pipeline
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Color space conversion (RGB to YUV and
YUV to RGB).
Programmable window size.
Chroma and color keying for integrated video
overlay.
Programmable two tap filter with gamma
correction or three tap flicker filter.
Progressive to interlaced scan converter.
Digital NTSC/PAL encoder
NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy
programmable video outputs.
CCIR601 encoding with programmable color
subcarrier frequencies.
Line skip/insert capability
Interlaced or non-interlaced operation mode.
625 lines/50Hz or 525 lines/60Hz 8 bit
multiplexed CB-Y-CR digital input.
CVBS and R,G,B simultaneous analog
outputs through 10-bit DACs.
Cross color reduction by specific trap filtering
on luma within CVBS flow.
Power down mode available on each DAC.

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