IS61LV6416 Integrated Silicon Solution, Inc., IS61LV6416 Datasheet - Page 7

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IS61LV6416

Manufacturer Part Number
IS61LV6416
Description
64k X 16 High-speed Cmos Static Ram With 3.3v Supply
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
Symbol
t
t
t
t
t
t
t
t
t
t
t
output loading specified in Figure 1a.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
WC
SCE
HA
SD
HD
HZWE
LZWE
AW
SA
PBW
PWE
1
(2)
(2)
/
t
PWE
2
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH/LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min. Max.
8
6
8
0
0
7
6
6
0
3
-8 ns
4
(1,3)
(Over Operating Range)
Min. Max.
10
8
8
0
0
8
8
6
0
3
-10 ns
5
Min. Max.
12
9
9
0
0
9
9
6
0
3
-12 ns
6
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
®
1
2
3
4
5
6
7
8
9
10
11
12

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