IS62C256AL Integrated Silicon Solution, Inc., IS62C256AL Datasheet - Page 8

• Manufacturer Part Number: IS62C256AL
• Description: 32k X 8 Low Power Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

AC WAVEFORMS
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
IS65C256AL
IS62C256AL
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE = V
8
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
ADDRESS
ADDRESS
D
D
OUT
WE
D
OE
CE
OUT
WE
D
OE
IN
CE
IN
LOW
LOW
LOW
t
SA
(OE is HIGH During Write Cycle)
(OE is LOW During Write Cycle)
DATA UNDEFINED
t
DATA UNDEFINED
SA
IH
.
VALID ADDRESS
t
t
AW
t
t
HZWE
AW
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
(1)
(1,2)
HIGH-Z
HIGH-Z
t
SD
t
DATA
SD
DATA
IN
IN
VALID
VALID
t
HD
t
t
HD
LZWE
t
LZWE
t
Integrated Silicon Solution, Inc.
HA
t
HA
CS_WR2.eps
CS_WR3.eps
07/12/07
Rev. C