MBM29LV800TE Fujitsu Microelectronics, Inc., MBM29LV800TE Datasheet - Page 24

• Manufacturer Part Number: MBM29LV800TE
• Description: 8m 1m X 8/512 K X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

DQ
Toggle Bit I
DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
The MBM29LV800TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
devices will result in DQ
is completed, DQ
gramming, the Toggle Bit I is valid after the rising edge of the fourth WE pulses in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulses sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 2 s and then stop
toggling with data unchanged. In erase, devices will erase all selected sectors except for ones that are protected.
If all selected sectors are protected, the chip will toggle the toggle bit for about 200 s and then drop back into
read mode, having data unchanged.
Either CE or OE toggling will cause DQ
DQ
See “Taggle Bit I during Embedded Algorithm Operation Timing Diagram” in “
Toggle Bit I timing specifications and diagrams.
DQ
these conditions, DQ
cycle was not successfully completed. Data Polling is the only operating function of devices under this condition.
The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and
WE pins will control the output disable functions as described in “MBM29LV800TE/BE User Bus Operations
(BYTE = V
The DQ
this case, the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
read valid data on DQ
will indicate a “1.” Please note that this is not a device failure condition since devices were incorrectly used. If
this occurs, reset device with command sequence.
After completion of the initial sector erase command sequence, sector erase time-out will begin. DQ
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ
used to determine if the sector erase timer window is still open. If DQ
cycle has begun : If DQ
command has been accepted, the system software should check the status of DQ
subsequent Sector Erase command. If DQ
been accepted.
See “Hardware Sequence Flags”.
6
5
3
6
5
to toggle.
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
5
failure condition may also appear if a user tries to program a non blank location without pre-erase. In
IH
)” and “MBM29LV800TE/BE User Bus Operations (BYTE = V
6
will stop toggling and valid data will be read on the next successive attempts. During pro-
5
7
will produce a “1”. This is a failure condition which indicates that the program or erase
6
bit and DQ
toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle
3
is low (“0”) , the device will accept additional sector erase commands. To insure the
6
never stop toggling. Once devices have exceeded timing limits, the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will cause
3
were high on the second status check, the command may not have
MBM29LV800TE/BE
3
is high (“1”) the internally controlled erase
IL
)” in “ DEVICE BUS OPERATION”.
3
TIMING DIAGRAM” for the
prior to and following each
3
will remain
60/70/90
3
may be
5
bit
23