MBM29LV001TC Fujitsu Microelectronics, Inc., MBM29LV001TC Datasheet - Page 22

• Manufacturer Part Number: MBM29LV001TC
• Description: 1m 128k X 8 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

22
MBM29LV001TC
Notes: 1. Performing successive read operations from any address will cause DQ
RESET
Hardware Reset
Data Protection
Low V
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
Erase-Suspend Program
The MBM29LV001TC/BC devices may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional t
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. See
Figure 12 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
The MBM29LV001TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 2.3 V (typically 2.4 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
CC
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
CC
Write Inhibit
level is greater than V
logic “1” at the DQ
toggle.
Mode
2
bit. However, successive reads from the erase-suspended sector will cause DQ
LKO
RH
CC
-55/-70
. It is the users responsibility to ensure that the control pins are logically correct
< V
before it will allow read access. When the RESET pin is low, the devices will
LKO
IL
, the command register is disabled and all internal program/erase circuits
CC
) for at least 500 ns in order to properly reset the internal state machine.
/MBM29LV001BC
is above 2.3 V.
CC
DQ
DQ
DQ
power-up and power-down, a write cycle is locked out for V
0
1
7
7
7
Toggle (Note 1)
Toggle
Toggle
DQ
1
6
-55/-70
IL
. The RESET pin has a pulse
6
to toggle.
1 (Note 2)
Toggle
Toggle
DQ
1
CC
2
power-up
CC
less
2
to