MBM29PL160TD-90PF Meet Spansion Inc., MBM29PL160TD-90PF Datasheet - Page 24

• Manufacturer Part Number: MBM29PL160TD-90PF
• Description: Page Mode Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit
• Manufacturer: Meet Spansion Inc.

24
MBM29PL160TD/BD
DQ
Data Polling
DQ
Toggle Bit I
The MBM29PL160TD/BD device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29PL160TD/BD data pins (DQ
enable (OE) is asserted low. This means that the device is driving status information on DQ
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ
output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ
to DQ
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out.
See "(6) AC Waveforms for Data Polling during Embedded Algorithm Operations" in ■TIMING DIAGRAM for
the Data Polling timing specifications and diagrams.
The MBM29PL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100 µs and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
cause the DQ
See "(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations" in ■TIMING DIAGRAM and
"(4) Toggle Bit Algorithm" in ■FLOW CHART for the Toggle Bit I timing specifications and diagrams.
7
6
0
will be read on successive read attempts.
6
to toggle.
7
has a valid data, the data outputs on DQ
7
) is shown in "(3) Data Polling Algorithm" (■FLOW CHART).
6
will stop toggling and valid data can be read on the next successive attempts. During
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
Retired Product DS05-20872-4E_July 31, 2007
-75/90
6
to toggle. In addition, an Erase Suspend/Resume command will
6
to DQ
7
7
) may change asynchronously while the output
. Upon completion of the Embedded Program
0
may be still invalid. The valid data on DQ
7
output. Upon completion of the
7
. During the Embedded
7
output. The flowchart
7
at one instant of
7
7