MBM29LV002TC-70 Meet Spansion Inc., MBM29LV002TC-70 Datasheet - Page 23

• Manufacturer Part Number: MBM29LV002TC-70
• Description: Flash Memory Cmos 2m 256k ? 8 Bit
• Manufacturer: Meet Spansion Inc.

RESET
Hardware Reset
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
The MBM29LV002TC/BC devices may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional t
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “ (9) RESET/RY/BY Timing
Diagram” in ■ TIMING DIAGRAM for the timing diagram. Refer to “Temporary Sector Unprotection” for additional
functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
The MBM29LV002TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 2.3 V (typically 2.4 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the devices with WE = CE = V
pulse. The internal state machine is automatically reset to the read mode on power-up.
CC
CC
Write Inhibit
level is greater than V
MBM29LV002TC
LKO
CC
RH
. It is the users responsibility to ensure that the control pins are logically correct
< V
before it will allow read access. When the RESET pin is low, the devices will
LKO
Retired Product DS05-20863-5E_July 26, 2007
IL
, the command register is disabled and all internal program/erase circuits
CC
) for at least 500 ns in order to properly reset the internal state machine.
is above 2.3 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
IL
, CE = V
IH
-70/-90
will not accept commands on the rising edge of write
IH
, or WE = V
/MBM29LV002BC
IH
. To initiate a write cycle CE and WE
IL
. The RESET pin has a pulse
CC
power-up
-70/-90
CC
less
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