TB31356AFL TOSHIBA Semiconductor CORPORATION, TB31356AFL Datasheet - Page 7

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TB31356AFL

Manufacturer Part Number
TB31356AFL
Description
1.8ghz,600mhz Dual-pll Frequency Synthesizer
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
l
A signal indicating whether the PLL has phase-locked to the desired frequency is presented to the LD pin.
The PLL to be detected in this way can be selected by setting two bits, LD1 and LD2, as shown in the table
below.
l
The PLL1, PLL2, and crystal oscillator circuit can be switched between operating and power-down
modes by using three bits—SB1, SB2, and SBX. The table below shows how operation is controlled by using
these bits and external battery save pins.
This specification is design target. It is subject to change without notice
Lock detection
Power-down mode
Locked in phase = open, Unlocked = low, Power-down mode = open
Notes1 : ON : operating, OFF : power-down (not operating), * : don’t care
Notes2 : Switching between operating and battery saving (power down) mode by using serial data is
Notes3 : Switching between operating and battery saving (power down) mode by using external pin
Notes4 : Immediately after power on, need a initial setting by serial data before operation state “ON”.
BS1
LD1
External Pin
H
H
H
H
H
H
L
L
0
0
1
1
renewed at the rising edge of strobe signal.
(BS-PLL1,BS-PLL2) is controlled real-time.
BS2
H
H
H
H
H
H
L
L
LD2
TENTATIVE
0
1
0
1
SB1
0
0
0
1
1
*
*
*
Only when both PLL1 and PLL2 are
Serial Data
SB2
0
0
1
0
1
*
*
*
Not detected (fixed low)
Detected PLL
SBX
detected
0
1
*
*
*
*
*
*
PLL2
PLL1
PLL1
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
Operation State
PLL2
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
.
Buffer
OFF
OFF
ON
ON
ON
ON
ON
ON
Nov. 27 2002 PAGE 7
TB31356AFL

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