APD-128G064D Vishay, APD-128G064D Datasheet - Page 2

• Manufacturer Part Number: APD-128G064D
• Description: 128 X 64 Graphics Display With Video Interface, Dc Converter, Drive Circuitry, Bright, Vivid Graphics, Powerful Software Commands, Flicker Free Screen, Slim Profile
• Manufacturer: Vishay

*NOTE: The maximum VDC draw denotes a power up condition
when the DC converter starts. Typical duration is 15-30 mS.
DESCRIPTION OF INPUT SIGNALS
DOT CLOCK: This signal enters the SERIAL DATA on each
low to high transition. A total of 128 DOT CLOCK transitions
must be present for each line of column/anode data.
SERIAL DATA: This signal presents the pixel data in
positive logic format. A logic one represents a lit pixel and a
logic zero represents an extinguished pixel. Data is entered
from right to left. The first pixel data entered will represent
the leftmost pixel in the row.
COLUMN LATCH: This signal latches the pixel data into the
driver outputs. When the COLUMN LATCH signal goes to
logic one the data entered previously will fall through to the
driver outputs. When the signal returns to a logic zero, the
data is latched and the shift register is now ready to accept
the next row of data. Must be held low while entering new
SERIAL DATA.
DISPLAY ENABLE: This signal enables the output drivers.
Using a duty cycle control, this signal may also be used for
intensity control. The DISPLAY ENABLE must be at logic
zero before the COLUMN LATCH signal transitions. To
avoid display blurring, the ROW CLOCK signal should also
transition while DISPLAY ENABLE is a logic zero. It is
recommended that this signal remain low for 10µS minutes.
ROW DATA: This signal is the first line marker for the scan.
This input should be held high to correspond to the first row
of pixel data.
ROW CLOCK: This signal clocks ROW DATA on the falling
edge. The ROW CLOCK signal is repetitive and must be
present for proper scanning of the display module.
The APD-128G064D has a unique input protection circuit
that assures the column drivers stay blanked on power up.
The protection circuit unblanks the column drivers when the
ROW CLOCK signal begins (i.e. the display begins scan-
ning).
This information is subject to change without notice.
Document Number: 37055
Revision 05-Dec-00
POWER SUPPLY: (Recommended)
POWER SUPPLY CONNECTION
CONNECTOR
J1
VDC
SIGNAL DESCRIPTION
PIN
1
3
5
7
9
11
*
+ 12 V ± 0.6 V
FUNCTION
DEm
Rdata
Rclk
latch
Dot CLK
Sdata
GND
PIN
1
2
3
4
DESCRIPTION
Display enable signal
Row driver data input
Row clock
Column latch
Dot clock
Serial column data
Common Ground
1.5 A Max.*, 0.4 A Typ.
SIGNAL
+ 12 VDC
GROUND
GROUND
N/C
LOGIC AND DATA TIMING
Dot Clock
ORDERING INFORMATION
Display
Enable
Serial Data
PARAMETER
t
t
t
t
t
t
t
DESCRIPTION
Display Unit ........................................................ APD-128G064D
Non-Glare Filter (Amber CP) ...................................... 280109-19
Video Controller (+ 5V) .................................................. PDS-500
Video Controller (+ 12V) ............................................. PDS-500-1
APPLICABLE MATING
CONNECTORS
TO POWER INPUT (P1) ........... MOLEX .................. 09-50-3081
Connector Kit 280108-05
TO LOGIC INPUT (P2) ............. MOLEX .................. 39-27-1146
Row Data
Display
Enable
Row Clock
Column
Latch
Row Clock
1
2
3
4
5
6
7
Vishay Dale Power
Vishay Dale Data
Connector Kit
280108-0
t
1
1st Bit of Row Will Appear in Leftmost Column
5
MINIMUM
0
t
0
t
6
16.6
5
130
0
75
25
75
75
5
1
ROBINSON NUGENT....IDS-C14PK-TC
1
1
Positive Edge x 192
MANUFACTURER PART NUMBER
2
t
2
2
2
TYPICAL
METHODE .................. 3300-108
MOLEX .................. 09-06-5087
1000
14.3
112
20
—
—
—
AMP ....................... 640428-8
AMP ...... 746195-2, 746582-2
3M .... 3314-5002, 3314-5202
APD-128G064D
t
4
t
3
126
62
MAXIMUM
62
127
200
Vishay Dale
t
7
PART NUMBER
—
—
—
—
—
—
63
63
www.vishay.com
0
0
UNITS
1
1
nS
uS
uS
Hz
nS
nS
nS
3