IR3081 International Rectifier Corp., IR3081 Datasheet - Page 18

• Manufacturer Part Number: IR3081
• Description: Xphasetm Vr 10 Control Ic
• Manufacturer: International Rectifier Corp.

DESIGN PROCEDURES - IR3081 AND IR3086 CHIPSET
IR3081 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR3081 generates a triangle waveform to synchronize the phase ICs, and the switching frequency
of the each phase converter equals the oscillator frequency, which is set by the external resistor R
the curve in Figure 13.
Soft Start Capacitor C
Because the capacitor C
over-current latch delay time, and power good delay time, they should be considered together while choosing
C
The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. After the
ENABLE pin voltage rises above 0.6V, there is a soft-start delay time
released to allow the soft start. The soft start time
zero to V
Once C
delay time
and (4) respectively.
If faster over-current protection is required, a resistor in series with the soft start capacitor C
reduce the over-current fault latch delay time t
Equation (1) for soft start capacitor C
while the equation for soft start delay time t
case values of charge and discharge current, R
VDAC Slew Rate Programming Capacitor C
The slew rate of VDAC down-slope SR
Equation (7), where I
compensate VDAC circuit and is determined by Equation (8). The slew rate of VDAC up-slope SR
SS/DEL
Page 18 of 39
SS/DEL
.
O.
t
t
VccPG
SS
can be programmed by an external capacitor, which is determined by Equation (1).
is chosen, the soft start delay time
from output voltage (V
C
t
t
t
t
R
VccPG
SSDEL
SSDEL
OCDEL
SS
SINK
SS
SS/DEL
/
/
DEL
DEL
SS/DEL
=
=
=
is the sink current of VDAC pin as shown in Figure 15. The resistor R
=
C
C
=
C
=
C
SS
SS
SS
. 0
and Resistor R
I
SS
CHG
/
/
/
I
09
I
DEL
DEL
DEL
programs four different time parameters, i.e. soft start delay time, soft start time,
CHG
/
DISCHG
DEL
V
−
O
*
( *
1 *
*
t
OCDEL
t
*
I
1 (
I
. 3
SS
3 .
CHG
DISCHG
. 0
SS/DEL
3 .
91
C
09
DOWN
I
=
=
−
O
CHG
SS
−
) in regulation to Power Good are fixed and shown in Equations (2), (3)
70
C
*
R
=
V
/
SS
I
SS
DEL
SS/DEL
70
O
C
DISCHG
*
and Equation (4) for power good delay time t
/
/
VDAC
SS/DEL
−
10
SS
DEL
DEL
*
can be programmed by the external capacitor C
SS/DEL
V
1
10
6
/
−
) 3 .
O
OCDEL
DEL
*
6
∗
t
1 *
−
10
SS
*
6
(Equation 2) is changed to Equation (6). Considering the worst
t
I
=
and Resistor R
=
SSDEL,
3 .
CHG
t
*
−
SS
6
C
. 0
represents the time during which converter voltage rises from
should be no grater than 10kΩ.
. 0
, and the resistor R
SS
09
09
)
/
=
DEL
−
C
the over-current fault latch delay time
t
OCDEL
6
SS
( *
70
*
/
C
10
. 3
DEL
*
SS
10
91
−
∗
6
/
*
−
6
DEL
VDAC
−
6
1 (
*
V
t
SSDEL,
10
3 .
O
70
−
−
−
6
. 1
R
*
10
) 3
SS
SS/DEL
after which the error amplifier output is
/
−
DEL
6
*
70
is determined by Equation (5).
*
10
−
6
)
(1)
(2)
(3)
(4)
VccPG
(5)
(6)
SS/DEL
VDAC
10/01
UP
OSC
t
are unchanged,
VDAC
IR3081
OCDEL
can be used to
is proportional
as defined in
/04
according to
is used to
, and the