ADN2890 Analog Devices, Inc., ADN2890 Datasheet

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ADN2890

Manufacturer Part Number
ADN2890
Description
3.3 V 2.7 Gb/s Limiting Amplifier
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
SFP reference design available
Input sensitivity: 3 mV p-p
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 2 mV to 13 mV
Rx signal strength indicator (RSSI):
Single-supply operation: 3.3 V
Low power dissipation: 130 mW
Available in space-saving 3 mm × 3 mm 16-lead LFCSP
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/12/48, GbE, Fibre Channel receivers
10GBASE-LX4 transceivers
WDM transponders
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SFF-8472 compliant average power measurement
C
F
R
F
ADN2880
PD_CATHODE
PD_VCC
FUNCTIONAL BLOCK DIAGRAM
PIN
NIN
CAZ1
50Ω
ADN2890
AVCC
0.01
50Ω
Figure 1.
µ
3kΩ
AVEE
F
CAZ2
V
REF
GENERAL DESCRIPTION
The ADN2890 is a high gain, limiting amplifier optimized for
use in SONET, Gigabit Ethernet (GbE), and Fibre Channel
optical receivers that accept input levels of up to 2.0 V p-p
differential and have 3 mV p-p differential input sensitivity. The
ADN2890 provides the receiver functions of quantization and
loss of signal (LOS) detection. The ADN2890 can easily operate
at up to 3.2 Gb/s to support LX4 transceivers.
The limiting amplifier also measures average received power
based on a direct measurement of the photodiode current with
better than 1 dB of accuracy over the entire input range of the
receiver. This eliminates the need for external average Rx power
detection circuitry in SFF-8472 compliant optical transceivers.
The ADN2890 limiting amplifier operates from a single 3.3 V
supply, has low power dissipation, and is available in a space-
saving 3 mm × 3 mm 16-lead lead frame chip scale package
(LFCSP).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
DETECTOR
RSSI/LOS
DRVCC
DRVCC
THRADJ
50Ω
DRVEE
SQUELCH
50Ω
LOS
RSSI_OUT
© 2004 Analog Devices, Inc. All rights reserved.
OUTP
OUTN
+V
10k
Limiting Amplifier
ADuC7020
3.3 V 2.7 Gb/s
ADN2890
www.analog.com

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ADN2890 Summary of contents

Page 1

... This eliminates the need for external average Rx power detection circuitry in SFF-8472 compliant optical transceivers. The ADN2890 limiting amplifier operates from a single 3.3 V supply, has low power dissipation, and is available in a space- saving 3 mm × 16-lead lead frame chip scale package (LFCSP) ...

Page 2

... ADN2890 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 LIMAMP ....................................................................................... 8 REVISION HISTORY Revision 0: Initial Version Loss of Signal (LOS) Detector .....................................................8 Received Signal Strength Indicator (RSSI).................................8 Squelch Mode ................................................................................8 Applications Information .................................................................9 PCB Design Guidelines ................................................................9 Outline Dimensions ...

Page 3

... OC-48, PRBS 2 − THRADJ ns DC-coupled ns DC-coupled µA ≤ 20 µ > 20 µA IN mA/ RSSI PD_CATHODE V mA ° MIN MAX Ω Single-ended V p-p Differential ps 20 2.4 V INH 0.4 V INL IN ADN2890 23 − − Ω = 100 kΩ ...

Page 4

... ADN2890 Parameter LOGIC OUTPUTS (LOS Output High Voltage Output Low Voltage OL Min Typ Max 2.4 0.4 Rev Page Unit Test Conditions/Comments V Open drain output, 4.7 kΩ − 10 kΩ pull-up resistor Open drain output, 4.7 kΩ − 10 kΩ pull-up resistor to V ...

Page 5

... THERMAL RESISTANCE 125°C θ is specified for 4-layer PCB with exposed paddle soldered JA to GND. Table 3. Package Type 16-lead 3 mm × LFCSP Rev Page ADN2890 θ Unit JA 28 °C/W ...

Page 6

... DRVEE 10 OUTN 11 OUTP 12 DRVCC 13 SQUELCH 14 RSSI_OUT 15 PD_VCC 16 PD_CATHODE Exposed Pad Pad AVCC DRVCC 1 12 ADN2890 PIN OUTP 2 11 TOP VIEW NIN OUTN 3 10 (Not To Scale) AVEE DRVEE Figure 2. Pin Configuration I/O Description Power Analog Power Input Differential Data Input ...

Page 7

... Figure 4. L Trip Point vs. Threshold Adjust Resistor 100k 1M SUPPLY-NOISE FREQUENCY (Hz) Figure 5. Typical PSRR vs. Supply-Noise Frequency 0.7 0.8 0.9 1.0 10k 100k 10M Rev Page VERTICAL SCALE: 100mV/DIV Figure 6. Eye Diagram at 3.2 Gb/s VERTICAL SCALE: 100mV/DIV Figure 7. Eye Diagram at 2.488 Gb/s ADN2890 ...

Page 8

... The ADN2890 has an on-chip RSSI circuit that automatically detects the average received power based on a direct measure- ment of the PIN photodiode’s current. The photodiode bias is supplied by the ADN2890, which allows a very accurate, on- chip, average power measurement based on the amount of current supplied to the photodiode. The output of the RSSI is a current that is directly proportional to the average amount of PIN photodiode current ...

Page 9

... PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2890 VCC pins. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 12, which supplies power to the high speed OUTP/OUTN output buffers ...

Page 10

... For supply decoupling, the 1 nF decoupling capacitor should be placed on the same layer as the ADN2890 as close as possible to the VCC pin. The 0.1 µF capacitor can be placed on the bottom of the PCB directly underneath the 1 nF decoupling capacitor ...

Page 11

... COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 10. 16-Lead Lead Frame Chip Scale Package [LFCSP × Body (CP-16-3) Dimensions shown in millimeters Package Description 16-LFCSP 16-LFCSP 16-LFCSP Rev Page 0.50 0.40 0.30 PIN 1 INDICATOR 1. 0.25 MIN Package Option Branding CP-16-3 F02 CP-16-3 F02 CP-16-3 F02 ADN2890 ...

Page 12

... ADN2890 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04509–0–5/04(0) Rev Page ...

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