ADN2807 Analog Devices, Inc., ADN2807 Datasheet - Page 13

• Manufacturer Part Number: ADN2807
• Description: 155/622 Mb/s Clock And Data Recovery Ic With Integrated Limiting Amp
• Manufacturer: Analog Devices, Inc.

The ADN2807 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate. The input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV
(e.g., LVPECL or LVDS) or a standard single-ended low voltage
TTL input, providing maximum system flexibility. The
appropriate division ratio can be selected using the REFSEL0/1
pins according to Table 6. Phase noise and duty cycle of the
reference clock are not critical, and 100 ppm accuracy is
sufficient.
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 7.
Table 6. Reference Frequency Selection
REFSEL
1
1
1
1
0
REFSEL[1..0]
00
01
10
11
XX
19.44MHz
Figure 17. Crystal Oscillator Configuration
REFCLKN
REFCLKP
NC
VCC
XO1
XO2
Applied Reference
Frequency (MHz)
19.44
38.88
77.76
155.52
REFCLKP/N Inactive. Use 19.44 MHz
XTAL on Pins XO1, XO2 (Pull REFCLKP
to VCC)
REFSEL
ADN2807
100kΩ
OSCILLATOR
CRYSTAL
100kΩ
BUFFER
VCC/2
1000
Figure 18. Transfer Function of LOL
500
Rev. A | Page 13 of 20
1
0
LOL
Table 7. Required Crystal Specifications
Parameter
Mode
Frequency/Overall Stability
Frequency Accuracy
Temperature Stability
Aging
ESR
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active or to VEE when the oscillator is used. No connection
between the XO pin and REFCLK input is necessary (Figure 15
to Figure 17). Note that the crystal should operate in series
resonant mode, which renders it insensitive to external
parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss-of-lock
signal when the VCO is within 500 ppm of center frequency.
This enables the phase loop, which then maintains phase lock,
unless the frequency error exceeds 0.1%. Should this occur, the
loss-of-lock signal is reasserted and control returns to the
frequency loop, which will reacquire and maintain a stable clock
signal at the output. The frequency loop requires a single
external capacitor between CF1 and CF2. The capacitor
specification is given in Table 8.
Table 8. Recommended C
Parameter
Temperature Range
Capacitance
Leakage
Rating
500
1000
f
(ppm)
VCO
ERROR
F
Capacitor Specification
Value
Series Resonant
±100 ppm
±100 ppm
±100 ppm
50 Ω max
19.44 MHz ± 100 ppm
Value
–40°C to +85°C
>3.0 µF
<80 nA
>6.3 V
ADN2807